2004-10-11 02:05:18 +09:00
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/*
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* i2c Support for Atmel's AT91RM9200 Two-Wire Interface
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*
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* (c) Rick Bronson
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*
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* Borrowed heavily from original work by:
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* Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
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*
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* Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <common.h>
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#ifdef CONFIG_HARD_I2C
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <at91rm9200_i2c.h>
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2004-12-15 08:28:24 +09:00
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/* define DEBUG */
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2004-10-11 02:05:18 +09:00
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/*
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* Poll the i2c status register until the specified bit is set.
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* Returns 0 if timed out (100 msec)
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*/
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static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) {
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int loop_cntr = 10000;
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do {
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2004-11-21 09:06:33 +09:00
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udelay(10);
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2004-10-11 02:05:18 +09:00
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} while (!(twi->TWI_SR & bit) && (--loop_cntr > 0));
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return (loop_cntr > 0);
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}
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/*
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* Generic i2c master transfer entrypoint
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*
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* rw == 1 means that this is a read
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*/
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static int
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at91_xfer(unsigned char chip, unsigned int addr, int alen,
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unsigned char *buffer, int len, int rw)
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{
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AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
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int length;
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unsigned char *buf;
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/* Set the TWI Master Mode Register */
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twi->TWI_MMR = (chip << 16) | (alen << 8)
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| ((rw == 1) ? AT91C_TWI_MREAD : 0);
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/* Set TWI Internal Address Register with first messages data field */
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if (alen > 0)
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2005-10-06 08:22:22 +09:00
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twi->TWI_IADR = addr;
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2004-10-11 02:05:18 +09:00
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length = len;
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buf = buffer;
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if (length && buf) { /* sanity check */
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if (rw) {
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twi->TWI_CR = AT91C_TWI_START;
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while (length--) {
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if (!length)
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twi->TWI_CR = AT91C_TWI_STOP;
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/* Wait until transfer is finished */
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if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) {
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2004-12-15 08:28:24 +09:00
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debug ("at91_i2c: timeout 1\n");
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2004-10-11 02:05:18 +09:00
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return 1;
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}
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*buf++ = twi->TWI_RHR;
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}
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if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
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2004-12-15 08:28:24 +09:00
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debug ("at91_i2c: timeout 2\n");
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2004-10-11 02:05:18 +09:00
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return 1;
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}
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} else {
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twi->TWI_CR = AT91C_TWI_START;
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while (length--) {
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twi->TWI_THR = *buf++;
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if (!length)
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twi->TWI_CR = AT91C_TWI_STOP;
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if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) {
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2004-12-15 08:28:24 +09:00
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debug ("at91_i2c: timeout 3\n");
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2004-10-11 02:05:18 +09:00
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return 1;
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}
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}
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/* Wait until transfer is finished */
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if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
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2004-12-15 08:28:24 +09:00
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debug ("at91_i2c: timeout 4\n");
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2004-10-11 02:05:18 +09:00
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return 1;
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}
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}
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}
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return 0;
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}
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int
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i2c_probe(unsigned char chip)
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{
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char buffer[1];
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return at91_xfer(chip, 0, 0, buffer, 1, 1);
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}
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int
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2005-04-03 23:18:51 +09:00
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i2c_read (unsigned char chip, unsigned int addr, int alen,
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unsigned char *buffer, int len)
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2004-10-11 02:05:18 +09:00
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{
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2004-10-11 03:03:33 +09:00
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#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
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2004-10-11 02:05:18 +09:00
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/* we only allow one address byte */
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if (alen > 1)
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return 1;
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/* XXX assume an ATMEL AT24C16 */
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if (alen == 1) {
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2004-10-11 03:03:33 +09:00
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#if 0 /* EEPROM code already sets this correctly */
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2004-10-11 02:05:18 +09:00
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chip |= (addr >> 8) & 0xff;
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2004-10-11 03:03:33 +09:00
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#endif
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2004-10-11 02:05:18 +09:00
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addr = addr & 0xff;
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}
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#endif
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return at91_xfer(chip, addr, alen, buffer, len, 1);
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}
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int
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i2c_write(unsigned char chip, unsigned int addr, int alen,
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2005-04-13 19:02:42 +09:00
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unsigned char *buffer, int len)
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2004-10-11 02:05:18 +09:00
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{
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2005-04-13 19:02:42 +09:00
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#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
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2004-10-11 02:05:18 +09:00
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int i;
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unsigned char *buf;
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/* we only allow one address byte */
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if (alen > 1)
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return 1;
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/* XXX assume an ATMEL AT24C16 */
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if (alen == 1) {
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buf = buffer;
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/* do single byte writes */
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for (i = 0; i < len; i++) {
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2004-10-11 03:03:33 +09:00
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#if 0 /* EEPROM code already sets this correctly */
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2004-10-11 02:05:18 +09:00
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chip |= (addr >> 8) & 0xff;
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2004-10-11 03:03:33 +09:00
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#endif
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2004-10-11 02:05:18 +09:00
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addr = addr & 0xff;
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if (at91_xfer(chip, addr, alen, buf++, 1, 0))
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return 1;
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2004-10-11 03:03:33 +09:00
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addr++;
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2004-10-11 02:05:18 +09:00
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}
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2004-10-11 03:03:33 +09:00
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return 0;
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2004-10-11 02:05:18 +09:00
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}
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#endif
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return at91_xfer(chip, addr, alen, buffer, len, 0);
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}
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/*
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* Main initialization routine
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*/
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void
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i2c_init(int speed, int slaveaddr)
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{
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AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
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*AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
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*AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
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*AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK;
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*AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */
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twi->TWI_IDR = 0x3ff; /* Disable all interrupts */
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twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */
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twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */
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/* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
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twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8);
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2004-12-15 08:28:24 +09:00
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debug ("Found AT91 i2c\n");
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2004-10-11 02:05:18 +09:00
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return;
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}
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2005-04-08 07:36:40 +09:00
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uchar i2c_reg_read(uchar i2c_addr, uchar reg)
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{
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char buf;
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i2c_read(i2c_addr, reg, 1, &buf, 1);
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return(buf);
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}
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void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
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{
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i2c_write(i2c_addr, reg, 1, &val, 1);
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}
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2004-10-11 02:05:18 +09:00
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#endif /* CONFIG_HARD_I2C */
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