mirror of
https://github.com/brain-hackers/u-boot-brain
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173 lines
4.1 KiB
C
173 lines
4.1 KiB
C
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/*
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* (C) Copyright 2001
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* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This provides a bit-banged interface to the ethernet MII management
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* channel.
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*/
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#include <common.h>
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#include <miiphy.h>
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#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
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/*****************************************************************************
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*
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* Read the OUI, manufacture's model number, and revision number.
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*
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* OUI: 22 bits (unsigned int)
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* Model: 6 bits (unsigned char)
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* Revision: 4 bits (unsigned char)
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*
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* Returns:
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* 0 on success
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*/
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int miiphy_info (unsigned char addr,
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unsigned int *oui,
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unsigned char *model, unsigned char *rev)
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{
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unsigned int reg = 0;
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/*
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* Trick: we are reading two 16 registers into a 32 bit variable
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* so we do a 16 read into the high order bits of the variable (big
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* endian, you know), shift it down 16 bits, and the read the rest.
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*/
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if (miiphy_read (addr, PHY_PHYIDR2, (unsigned short *) ®) != 0) {
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#ifdef DEBUG
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printf ("PHY ID register 2 read failed\n");
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#endif
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return (-1);
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}
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reg >>= 16;
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#ifdef DEBUG
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printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
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#endif
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if (reg == 0xFFFF) {
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/* No physical device present at this address */
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return (-1);
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}
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if (miiphy_read (addr, PHY_PHYIDR1, (unsigned short *) ®) != 0) {
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#ifdef DEBUG
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printf ("PHY ID register 1 read failed\n");
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#endif
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return (-1);
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}
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#ifdef DEBUG
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printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
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#endif
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*oui = ( reg >> 10);
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*model = (unsigned char) ((reg >> 4) & 0x0000003F);
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*rev = (unsigned char) ( reg & 0x0000000F);
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return (0);
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}
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/*****************************************************************************
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*
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* Reset the PHY.
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* Returns:
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* 0 on success
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*/
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int miiphy_reset (unsigned char addr)
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{
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unsigned short reg;
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int loop_cnt;
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if (miiphy_write (addr, PHY_BMCR, 0x8000) != 0) {
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#ifdef DEBUG
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printf ("PHY reset failed\n");
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#endif
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return (-1);
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}
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/*
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* Poll the control register for the reset bit to go to 0 (it is
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* auto-clearing). This should happen within 0.5 seconds per the
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* IEEE spec.
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*/
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loop_cnt = 0;
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reg = 0x8000;
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while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
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if (miiphy_read (addr, PHY_BMCR, ®) != 0) {
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# ifdef DEBUG
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printf ("PHY status read failed\n");
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# endif
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return (-1);
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}
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}
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if ((reg & 0x8000) == 0) {
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return (0);
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} else {
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printf ("PHY reset timed out\n");
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return (-1);
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}
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return (0);
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}
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/*****************************************************************************
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*
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* Determine the ethernet speed (10/100).
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*/
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int miiphy_speed (unsigned char addr)
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{
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unsigned short reg;
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if (miiphy_read (addr, PHY_ANLPAR, ®)) {
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printf ("PHY speed1 read failed, assuming 10bT\n");
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return (_10BASET);
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}
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if ((reg & PHY_ANLPAR_100) != 0) {
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return (_100BASET);
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} else {
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return (_10BASET);
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}
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}
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/*****************************************************************************
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*
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* Determine full/half duplex.
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*/
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int miiphy_duplex (unsigned char addr)
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{
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unsigned short reg;
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if (miiphy_read (addr, PHY_ANLPAR, ®)) {
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printf ("PHY duplex read failed, assuming half duplex\n");
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return (HALF);
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}
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if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
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return (FULL);
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} else {
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return (HALF);
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}
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}
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#endif /* CONFIG_MII || (CONFIG_COMMANDS & CFG_CMD_MII) */
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