2012-12-11 22:34:12 +09:00
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/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _TEGRA_GP_PADCTRL_H_
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#define _TEGRA_GP_PADCTRL_H_
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#define GP_HIDREV 0x804
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/* bit fields definitions for APB_MISC_GP_HIDREV register */
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#define HIDREV_CHIPID_SHIFT 8
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#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
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#define HIDREV_MAJORPREV_SHIFT 4
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#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
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/* CHIPID field returned from APB_MISC_GP_HIDREV register */
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#define CHIPID_TEGRA20 0x20
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#define CHIPID_TEGRA30 0x30
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2013-01-28 22:32:07 +09:00
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#define CHIPID_TEGRA114 0x35
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2012-12-11 22:34:12 +09:00
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#endif /* _TEGRA_GP_PADCTRL_H_ */
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