u-boot-brain/arch/x86/include/asm/arch-braswell/iomap.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
 */

#ifndef _BRASWELL_IOMAP_H_
#define _BRASWELL_IOMAP_H_

/* Memory Mapped IO bases */

/* Power Management Controller */
#define PMC_BASE_ADDRESS	0xfed03000
#define PMC_BASE_SIZE		0x400

/* Power Management Unit */
#define PUNIT_BASE_ADDRESS	0xfed05000
#define PUNIT_BASE_SIZE		0x800

/* Intel Legacy Block */
#define ILB_BASE_ADDRESS	0xfed08000
#define ILB_BASE_SIZE		0x400

/* SPI Bus */
#define SPI_BASE_ADDRESS	0xfed01000
#define SPI_BASE_SIZE		0x400

/* Root Complex Base Address */
#define RCBA_BASE_ADDRESS	0xfed1c000
#define RCBA_BASE_SIZE		0x400

/* IO Memory */
#define IO_BASE_ADDRESS		0xfed80000
#define IO_BASE_SIZE		0x4000

/* MODPHY */
#define MPHY_BASE_ADDRESS	0xfef00000
#define MPHY_BASE_SIZE		0x100000

/* IO Port bases */

#define ACPI_BASE_ADDRESS	0x400
#define ACPI_BASE_SIZE		0x80

#define GPIO_BASE_ADDRESS	0x500
#define GPIO_BASE_SIZE		0x100

#define SMBUS_BASE_ADDRESS	0xefa0

#endif /* _BRASWELL_IOMAP_H_ */
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-07 06:58:06 +09:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
x86: Add Intel Braswell SoC support This adds initial Intel Braswell SoC support. It uses Intel FSP to initialize the chipset. Similar to its predecessor BayTrail, there are some work to do to enable the legacy UART integrated in the Braswell SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 2017-08-16 14:41:58 +09:00			`/*`
			`* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>`
			`*/`

			`#ifndef _BRASWELL_IOMAP_H_`
			`#define _BRASWELL_IOMAP_H_`

			`/* Memory Mapped IO bases */`

			`/* Power Management Controller */`
			`#define PMC_BASE_ADDRESS 0xfed03000`
			`#define PMC_BASE_SIZE 0x400`

			`/* Power Management Unit */`
			`#define PUNIT_BASE_ADDRESS 0xfed05000`
			`#define PUNIT_BASE_SIZE 0x800`

			`/* Intel Legacy Block */`
			`#define ILB_BASE_ADDRESS 0xfed08000`
			`#define ILB_BASE_SIZE 0x400`

			`/* SPI Bus */`
			`#define SPI_BASE_ADDRESS 0xfed01000`
			`#define SPI_BASE_SIZE 0x400`

			`/* Root Complex Base Address */`
			`#define RCBA_BASE_ADDRESS 0xfed1c000`
			`#define RCBA_BASE_SIZE 0x400`

			`/* IO Memory */`
			`#define IO_BASE_ADDRESS 0xfed80000`
			`#define IO_BASE_SIZE 0x4000`

			`/* MODPHY */`
			`#define MPHY_BASE_ADDRESS 0xfef00000`
			`#define MPHY_BASE_SIZE 0x100000`

			`/* IO Port bases */`

			`#define ACPI_BASE_ADDRESS 0x400`
			`#define ACPI_BASE_SIZE 0x80`

			`#define GPIO_BASE_ADDRESS 0x500`
			`#define GPIO_BASE_SIZE 0x100`

			`#define SMBUS_BASE_ADDRESS 0xefa0`

			`#endif /* _BRASWELL_IOMAP_H_ */`