u-boot-brain/arch/arm/mach-sunxi/dram_timings/Makefile

obj-$(CONFIG_SUNXI_DRAM_DDR3_1333)	+= ddr3_1333.o
obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK)	+= lpddr3_stock.o
obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S)	+= ddr2_v3s.o
obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3)	+= h6_lpddr3.o
obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333)	+= h6_ddr3_1333.o
sunxi: Add selective DRAM type and timing DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> 2017-06-03 18:10:18 +09:00			`obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o`
sunxi: add LPDDR3 timing from stock boot0 As we added LPDDR3 support in the former patch, we need a set of timing info to really enable it. Add the timing info used by stock boot0. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> 2017-06-03 18:10:24 +09:00			`obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o`
sunxi: add support for the DDR2 in V3s SoC Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its timing param. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> 2017-06-03 18:10:20 +09:00			`obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o`
sunxi: H6: move LPDDR3 timing definition into separate file Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM. Split the timing parameters for this LPDDR3 configuration into a separate file, to allow selecting an alternative later at compile time (as the sunxi-dw driver does). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 2019-07-15 10:27:06 +09:00			`obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3) += h6_lpddr3.o`
sunxi: H6: Add DDR3-1333 timings Add a routine to program the timing parameters for DDR3-1333 DRAM chips connected to the H6 DRAM controller. The values were gathered from doing back-calculations from a register dump, trying to match them up with the official JEDEC DDDR3 spec. If in doubt, the register dump values were taken for now, but the JEDEC recommendation were added as a comment. Many thanks to Jernej for contributing fixes! Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 2019-07-15 10:27:08 +09:00			`obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o`