u-boot-brain/configs/qemu-riscv32_spl_defconfig

CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_CMD_MII is not set
CONFIG_OF_PRIOR_STAGE=y
riscv: qemu: add SPL configuration Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The configurations are meant to help the development of SPL on RISC-V. The configurations enable RAM as the only SPL boot device. Images must be loaded at address 0x80200000. In the default boot flow, U-Boot SPL starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is then started in supervisor mode by OpenSBI. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> 2019-08-22 04:14:49 +09:00			`CONFIG_RISCV=y`
			`CONFIG_NR_DRAM_BANKS=1`
			`CONFIG_SPL=y`
			`CONFIG_TARGET_QEMU_VIRT=y`
			`CONFIG_RISCV_SMODE=y`
			`CONFIG_DISTRO_DEFAULTS=y`
			`CONFIG_FIT=y`
			`CONFIG_DISPLAY_CPUINFO=y`
			`CONFIG_DISPLAY_BOARDINFO=y`
			`# CONFIG_CMD_MII is not set`
			`CONFIG_OF_PRIOR_STAGE=y`