mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-09 22:33:28 +09:00
1054 lines
27 KiB
C
1054 lines
27 KiB
C
![]() |
/*
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* Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* Copyright (C) 2014 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <usb.h>
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#include <malloc.h>
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#include <usbroothubdes.h>
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#include <asm/io.h>
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#include "dwc2.h"
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/* Use only HC channel 0. */
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#define DWC2_HC_CHANNEL 0
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#define DWC2_STATUS_BUF_SIZE 64
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#define DWC2_DATA_BUF_SIZE (64 * 1024)
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/* We need doubleword-aligned buffers for DMA transfers */
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DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, 8);
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DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, 8);
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#define MAX_DEVICE 16
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#define MAX_ENDPOINT 16
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static int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
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static int control_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
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static int root_hub_devnum;
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static struct dwc2_core_regs *regs =
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(struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
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/*
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* DWC2 IP interface
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*/
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static int wait_for_bit(void *reg, const uint32_t mask, bool set)
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{
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unsigned int timeout = 1000000;
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uint32_t val;
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while (--timeout) {
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val = readl(reg);
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if (!set)
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val = ~val;
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if ((val & mask) == mask)
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return 0;
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udelay(1);
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}
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debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
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__func__, reg, mask, set);
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return -ETIMEDOUT;
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}
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/*
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* Initializes the FSLSPClkSel field of the HCFG register
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* depending on the PHY type.
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*/
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static void init_fslspclksel(struct dwc2_core_regs *regs)
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{
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uint32_t phyclk;
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#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
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phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
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#else
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/* High speed PHY running at full speed or high speed */
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phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
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#endif
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#ifdef CONFIG_DWC2_ULPI_FS_LS
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uint32_t hwcfg2 = readl(®s->ghwcfg2);
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uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
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DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
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uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
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DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
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if (hval == 2 && fval == 1)
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phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
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#endif
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clrsetbits_le32(®s->host_regs.hcfg,
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DWC2_HCFG_FSLSPCLKSEL_MASK,
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phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
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}
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/*
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* Flush a Tx FIFO.
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*
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* @param regs Programming view of DWC_otg controller.
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* @param num Tx FIFO to flush.
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*/
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static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
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{
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int ret;
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writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
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®s->grstctl);
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ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
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if (ret)
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printf("%s: Timeout!\n", __func__);
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/* Wait for 3 PHY Clocks */
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udelay(1);
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}
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/*
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* Flush Rx FIFO.
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*
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* @param regs Programming view of DWC_otg controller.
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*/
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static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
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{
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int ret;
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writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
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ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
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if (ret)
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printf("%s: Timeout!\n", __func__);
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/* Wait for 3 PHY Clocks */
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udelay(1);
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}
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/*
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* Do core a soft reset of the core. Be careful with this because it
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* resets all the internal state machines of the core.
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*/
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static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
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{
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int ret;
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/* Wait for AHB master IDLE state. */
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ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
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if (ret)
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printf("%s: Timeout!\n", __func__);
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/* Core Soft Reset */
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writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
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ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
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if (ret)
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printf("%s: Timeout!\n", __func__);
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/*
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* Wait for core to come out of reset.
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* NOTE: This long sleep is _very_ important, otherwise the core will
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* not stay in host mode after a connector ID change!
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*/
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mdelay(100);
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}
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/*
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* This function initializes the DWC_otg controller registers for
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* host mode.
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*
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* This function flushes the Tx and Rx FIFOs and it flushes any entries in the
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* request queues. Host channels are reset to ensure that they are ready for
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* performing transfers.
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*
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* @param regs Programming view of DWC_otg controller
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*
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*/
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static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
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{
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uint32_t nptxfifosize = 0;
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uint32_t ptxfifosize = 0;
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uint32_t hprt0 = 0;
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int i, ret, num_channels;
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/* Restart the Phy Clock */
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writel(0, ®s->pcgcctl);
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/* Initialize Host Configuration Register */
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init_fslspclksel(regs);
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#ifdef CONFIG_DWC2_DFLT_SPEED_FULL
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setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
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#endif
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/* Configure data FIFO sizes */
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#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
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if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
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/* Rx FIFO */
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writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
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/* Non-periodic Tx FIFO */
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nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
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DWC2_FIFOSIZE_DEPTH_OFFSET;
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nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
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DWC2_FIFOSIZE_STARTADDR_OFFSET;
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writel(nptxfifosize, ®s->gnptxfsiz);
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/* Periodic Tx FIFO */
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ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
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DWC2_FIFOSIZE_DEPTH_OFFSET;
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ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
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CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
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DWC2_FIFOSIZE_STARTADDR_OFFSET;
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writel(ptxfifosize, ®s->hptxfsiz);
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}
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#endif
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/* Clear Host Set HNP Enable in the OTG Control Register */
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clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
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/* Make sure the FIFOs are flushed. */
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dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
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dwc_otg_flush_rx_fifo(regs);
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/* Flush out any leftover queued requests. */
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num_channels = readl(®s->ghwcfg2);
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num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
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num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
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num_channels += 1;
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for (i = 0; i < num_channels; i++)
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clrsetbits_le32(®s->hc_regs[i].hcchar,
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DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
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DWC2_HCCHAR_CHDIS);
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/* Halt all channels to put them into a known state. */
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for (i = 0; i < num_channels; i++) {
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clrsetbits_le32(®s->hc_regs[i].hcchar,
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DWC2_HCCHAR_EPDIR,
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DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
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ret = wait_for_bit(®s->hc_regs[i].hcchar,
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DWC2_HCCHAR_CHEN, 0);
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if (ret)
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printf("%s: Timeout!\n", __func__);
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}
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/* Turn on the vbus power. */
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if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
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hprt0 = readl(®s->hprt0);
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hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
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hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
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if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
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hprt0 |= DWC2_HPRT0_PRTPWR;
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writel(hprt0, ®s->hprt0);
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}
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}
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}
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/*
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* This function initializes the DWC_otg controller registers and
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* prepares the core for device mode or host mode operation.
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*
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* @param regs Programming view of the DWC_otg controller
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*/
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static void dwc_otg_core_init(struct dwc2_core_regs *regs)
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{
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uint32_t ahbcfg = 0;
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uint32_t usbcfg = 0;
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uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
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/* Common Initialization */
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usbcfg = readl(®s->gusbcfg);
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/* Program the ULPI External VBUS bit if needed */
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#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
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usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
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#else
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usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
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#endif
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/* Set external TS Dline pulsing */
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#ifdef CONFIG_DWC2_TS_DLINE
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usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
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#else
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usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
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#endif
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writel(usbcfg, ®s->gusbcfg);
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/* Reset the Controller */
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dwc_otg_core_reset(regs);
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/*
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* This programming sequence needs to happen in FS mode before
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* any other programming occurs
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*/
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#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
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(CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
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/* If FS mode with FS PHY */
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setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
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/* Reset after a PHY select */
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dwc_otg_core_reset(regs);
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/*
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* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
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* Also do this on HNP Dev/Host mode switches (done in dev_init
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* and host_init).
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*/
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if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
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init_fslspclksel(regs);
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#ifdef CONFIG_DWC2_I2C_ENABLE
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/* Program GUSBCFG.OtgUtmifsSel to I2C */
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setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
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/* Program GI2CCTL.I2CEn */
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clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
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DWC2_GI2CCTL_I2CDEVADDR_MASK,
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1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
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setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
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#endif
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#else
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/* High speed PHY. */
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/*
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* HS PHY parameters. These parameters are preserved during
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* soft reset so only program the first time. Do a soft reset
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* immediately after setting phyif.
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*/
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usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
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usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
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if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
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#ifdef CONFIG_DWC2_PHY_ULPI_DDR
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usbcfg |= DWC2_GUSBCFG_DDRSEL;
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#else
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usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
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#endif
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} else { /* UTMI+ interface */
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#if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
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usbcfg |= DWC2_GUSBCFG_PHYIF;
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#endif
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}
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writel(usbcfg, ®s->gusbcfg);
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/* Reset after setting the PHY parameters */
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dwc_otg_core_reset(regs);
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#endif
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usbcfg = readl(®s->gusbcfg);
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usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
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#ifdef CONFIG_DWC2_ULPI_FS_LS
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uint32_t hwcfg2 = readl(®s->ghwcfg2);
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uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
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DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
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uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
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DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
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if (hval == 2 && fval == 1) {
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usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
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usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
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}
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#endif
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writel(usbcfg, ®s->gusbcfg);
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/* Program the GAHBCFG Register. */
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switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
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case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
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break;
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case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
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while (brst_sz > 1) {
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ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
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ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
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brst_sz >>= 1;
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}
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#ifdef CONFIG_DWC2_DMA_ENABLE
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ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
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#endif
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break;
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case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
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ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
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#ifdef CONFIG_DWC2_DMA_ENABLE
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ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
|
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#endif
|
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break;
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}
|
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writel(ahbcfg, ®s->gahbcfg);
|
||
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|
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/* Program the GUSBCFG register for HNP/SRP. */
|
||
|
setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
|
||
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||
|
#ifdef CONFIG_DWC2_IC_USB_CAP
|
||
|
setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
|
||
|
#endif
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Prepares a host channel for transferring packets to/from a specific
|
||
|
* endpoint. The HCCHARn register is set up with the characteristics specified
|
||
|
* in _hc. Host channel interrupts that may need to be serviced while this
|
||
|
* transfer is in progress are enabled.
|
||
|
*
|
||
|
* @param regs Programming view of DWC_otg controller
|
||
|
* @param hc Information needed to initialize the host channel
|
||
|
*/
|
||
|
static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
|
||
|
uint8_t dev_addr, uint8_t ep_num, uint8_t ep_is_in,
|
||
|
uint8_t ep_type, uint16_t max_packet)
|
||
|
{
|
||
|
struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
|
||
|
const uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
|
||
|
(ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
|
||
|
(ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
|
||
|
(ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
|
||
|
(max_packet << DWC2_HCCHAR_MPS_OFFSET);
|
||
|
|
||
|
/* Clear old interrupt conditions for this host channel. */
|
||
|
writel(0x3fff, &hc_regs->hcint);
|
||
|
|
||
|
/*
|
||
|
* Program the HCCHARn register with the endpoint characteristics
|
||
|
* for the current transfer.
|
||
|
*/
|
||
|
writel(hcchar, &hc_regs->hcchar);
|
||
|
|
||
|
/* Program the HCSPLIT register for SPLITs */
|
||
|
writel(0, &hc_regs->hcsplt);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* DWC2 to USB API interface
|
||
|
*/
|
||
|
/* Direction: In ; Request: Status */
|
||
|
static int dwc_otg_submit_rh_msg_in_status(struct usb_device *dev, void *buffer,
|
||
|
int txlen, struct devrequest *cmd)
|
||
|
{
|
||
|
uint32_t hprt0 = 0;
|
||
|
uint32_t port_status = 0;
|
||
|
uint32_t port_change = 0;
|
||
|
int len = 0;
|
||
|
int stat = 0;
|
||
|
|
||
|
switch (cmd->requesttype & ~USB_DIR_IN) {
|
||
|
case 0:
|
||
|
*(uint16_t *)buffer = cpu_to_le16(1);
|
||
|
len = 2;
|
||
|
break;
|
||
|
case USB_RECIP_INTERFACE:
|
||
|
case USB_RECIP_ENDPOINT:
|
||
|
*(uint16_t *)buffer = cpu_to_le16(0);
|
||
|
len = 2;
|
||
|
break;
|
||
|
case USB_TYPE_CLASS:
|
||
|
*(uint32_t *)buffer = cpu_to_le32(0);
|
||
|
len = 4;
|
||
|
break;
|
||
|
case USB_RECIP_OTHER | USB_TYPE_CLASS:
|
||
|
hprt0 = readl(®s->hprt0);
|
||
|
if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
|
||
|
port_status |= USB_PORT_STAT_CONNECTION;
|
||
|
if (hprt0 & DWC2_HPRT0_PRTENA)
|
||
|
port_status |= USB_PORT_STAT_ENABLE;
|
||
|
if (hprt0 & DWC2_HPRT0_PRTSUSP)
|
||
|
port_status |= USB_PORT_STAT_SUSPEND;
|
||
|
if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
|
||
|
port_status |= USB_PORT_STAT_OVERCURRENT;
|
||
|
if (hprt0 & DWC2_HPRT0_PRTRST)
|
||
|
port_status |= USB_PORT_STAT_RESET;
|
||
|
if (hprt0 & DWC2_HPRT0_PRTPWR)
|
||
|
port_status |= USB_PORT_STAT_POWER;
|
||
|
|
||
|
port_status |= USB_PORT_STAT_HIGH_SPEED;
|
||
|
|
||
|
if (hprt0 & DWC2_HPRT0_PRTENCHNG)
|
||
|
port_change |= USB_PORT_STAT_C_ENABLE;
|
||
|
if (hprt0 & DWC2_HPRT0_PRTCONNDET)
|
||
|
port_change |= USB_PORT_STAT_C_CONNECTION;
|
||
|
if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
|
||
|
port_change |= USB_PORT_STAT_C_OVERCURRENT;
|
||
|
|
||
|
*(uint32_t *)buffer = cpu_to_le32(port_status |
|
||
|
(port_change << 16));
|
||
|
len = 4;
|
||
|
break;
|
||
|
default:
|
||
|
puts("unsupported root hub command\n");
|
||
|
stat = USB_ST_STALLED;
|
||
|
}
|
||
|
|
||
|
dev->act_len = min(len, txlen);
|
||
|
dev->status = stat;
|
||
|
|
||
|
return stat;
|
||
|
}
|
||
|
|
||
|
/* Direction: In ; Request: Descriptor */
|
||
|
static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
|
||
|
void *buffer, int txlen,
|
||
|
struct devrequest *cmd)
|
||
|
{
|
||
|
unsigned char data[32];
|
||
|
uint32_t dsc;
|
||
|
int len = 0;
|
||
|
int stat = 0;
|
||
|
uint16_t wValue = cpu_to_le16(cmd->value);
|
||
|
uint16_t wLength = cpu_to_le16(cmd->length);
|
||
|
|
||
|
switch (cmd->requesttype & ~USB_DIR_IN) {
|
||
|
case 0:
|
||
|
switch (wValue & 0xff00) {
|
||
|
case 0x0100: /* device descriptor */
|
||
|
len = min3(txlen, sizeof(root_hub_dev_des), wLength);
|
||
|
memcpy(buffer, root_hub_dev_des, len);
|
||
|
break;
|
||
|
case 0x0200: /* configuration descriptor */
|
||
|
len = min3(txlen, sizeof(root_hub_config_des), wLength);
|
||
|
memcpy(buffer, root_hub_config_des, len);
|
||
|
break;
|
||
|
case 0x0300: /* string descriptors */
|
||
|
switch (wValue & 0xff) {
|
||
|
case 0x00:
|
||
|
len = min3(txlen, sizeof(root_hub_str_index0),
|
||
|
wLength);
|
||
|
memcpy(buffer, root_hub_str_index0, len);
|
||
|
break;
|
||
|
case 0x01:
|
||
|
len = min3(txlen, sizeof(root_hub_str_index1),
|
||
|
wLength);
|
||
|
memcpy(buffer, root_hub_str_index1, len);
|
||
|
break;
|
||
|
}
|
||
|
break;
|
||
|
default:
|
||
|
stat = USB_ST_STALLED;
|
||
|
}
|
||
|
break;
|
||
|
|
||
|
case USB_TYPE_CLASS:
|
||
|
/* Root port config, set 1 port and nothing else. */
|
||
|
dsc = 0x00000001;
|
||
|
|
||
|
data[0] = 9; /* min length; */
|
||
|
data[1] = 0x29;
|
||
|
data[2] = dsc & RH_A_NDP;
|
||
|
data[3] = 0;
|
||
|
if (dsc & RH_A_PSM)
|
||
|
data[3] |= 0x1;
|
||
|
if (dsc & RH_A_NOCP)
|
||
|
data[3] |= 0x10;
|
||
|
else if (dsc & RH_A_OCPM)
|
||
|
data[3] |= 0x8;
|
||
|
|
||
|
/* corresponds to data[4-7] */
|
||
|
data[5] = (dsc & RH_A_POTPGT) >> 24;
|
||
|
data[7] = dsc & RH_B_DR;
|
||
|
if (data[2] < 7) {
|
||
|
data[8] = 0xff;
|
||
|
} else {
|
||
|
data[0] += 2;
|
||
|
data[8] = (dsc & RH_B_DR) >> 8;
|
||
|
data[9] = 0xff;
|
||
|
data[10] = data[9];
|
||
|
}
|
||
|
|
||
|
len = min3(txlen, data[0], wLength);
|
||
|
memcpy(buffer, data, len);
|
||
|
break;
|
||
|
default:
|
||
|
puts("unsupported root hub command\n");
|
||
|
stat = USB_ST_STALLED;
|
||
|
}
|
||
|
|
||
|
dev->act_len = min(len, txlen);
|
||
|
dev->status = stat;
|
||
|
|
||
|
return stat;
|
||
|
}
|
||
|
|
||
|
/* Direction: In ; Request: Configuration */
|
||
|
static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
|
||
|
void *buffer, int txlen,
|
||
|
struct devrequest *cmd)
|
||
|
{
|
||
|
int len = 0;
|
||
|
int stat = 0;
|
||
|
|
||
|
switch (cmd->requesttype & ~USB_DIR_IN) {
|
||
|
case 0:
|
||
|
*(uint8_t *)buffer = 0x01;
|
||
|
len = 1;
|
||
|
break;
|
||
|
default:
|
||
|
puts("unsupported root hub command\n");
|
||
|
stat = USB_ST_STALLED;
|
||
|
}
|
||
|
|
||
|
dev->act_len = min(len, txlen);
|
||
|
dev->status = stat;
|
||
|
|
||
|
return stat;
|
||
|
}
|
||
|
|
||
|
/* Direction: In */
|
||
|
static int dwc_otg_submit_rh_msg_in(struct usb_device *dev,
|
||
|
void *buffer, int txlen,
|
||
|
struct devrequest *cmd)
|
||
|
{
|
||
|
switch (cmd->request) {
|
||
|
case USB_REQ_GET_STATUS:
|
||
|
return dwc_otg_submit_rh_msg_in_status(dev, buffer,
|
||
|
txlen, cmd);
|
||
|
case USB_REQ_GET_DESCRIPTOR:
|
||
|
return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
|
||
|
txlen, cmd);
|
||
|
case USB_REQ_GET_CONFIGURATION:
|
||
|
return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
|
||
|
txlen, cmd);
|
||
|
default:
|
||
|
puts("unsupported root hub command\n");
|
||
|
return USB_ST_STALLED;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/* Direction: Out */
|
||
|
static int dwc_otg_submit_rh_msg_out(struct usb_device *dev,
|
||
|
void *buffer, int txlen,
|
||
|
struct devrequest *cmd)
|
||
|
{
|
||
|
int len = 0;
|
||
|
int stat = 0;
|
||
|
uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
|
||
|
uint16_t wValue = cpu_to_le16(cmd->value);
|
||
|
|
||
|
switch (bmrtype_breq & ~USB_DIR_IN) {
|
||
|
case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
|
||
|
case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
|
||
|
break;
|
||
|
|
||
|
case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
|
||
|
switch (wValue) {
|
||
|
case USB_PORT_FEAT_C_CONNECTION:
|
||
|
setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
|
||
|
break;
|
||
|
}
|
||
|
break;
|
||
|
|
||
|
case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
|
||
|
switch (wValue) {
|
||
|
case USB_PORT_FEAT_SUSPEND:
|
||
|
break;
|
||
|
|
||
|
case USB_PORT_FEAT_RESET:
|
||
|
clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
|
||
|
DWC2_HPRT0_PRTCONNDET |
|
||
|
DWC2_HPRT0_PRTENCHNG |
|
||
|
DWC2_HPRT0_PRTOVRCURRCHNG,
|
||
|
DWC2_HPRT0_PRTRST);
|
||
|
mdelay(50);
|
||
|
clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
|
||
|
break;
|
||
|
|
||
|
case USB_PORT_FEAT_POWER:
|
||
|
clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
|
||
|
DWC2_HPRT0_PRTCONNDET |
|
||
|
DWC2_HPRT0_PRTENCHNG |
|
||
|
DWC2_HPRT0_PRTOVRCURRCHNG,
|
||
|
DWC2_HPRT0_PRTRST);
|
||
|
break;
|
||
|
|
||
|
case USB_PORT_FEAT_ENABLE:
|
||
|
break;
|
||
|
}
|
||
|
break;
|
||
|
case (USB_REQ_SET_ADDRESS << 8):
|
||
|
root_hub_devnum = wValue;
|
||
|
break;
|
||
|
case (USB_REQ_SET_CONFIGURATION << 8):
|
||
|
break;
|
||
|
default:
|
||
|
puts("unsupported root hub command\n");
|
||
|
stat = USB_ST_STALLED;
|
||
|
}
|
||
|
|
||
|
len = min(len, txlen);
|
||
|
|
||
|
dev->act_len = len;
|
||
|
dev->status = stat;
|
||
|
|
||
|
return stat;
|
||
|
}
|
||
|
|
||
|
static int dwc_otg_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
|
||
|
void *buffer, int txlen,
|
||
|
struct devrequest *cmd)
|
||
|
{
|
||
|
int stat = 0;
|
||
|
|
||
|
if (usb_pipeint(pipe)) {
|
||
|
puts("Root-Hub submit IRQ: NOT implemented\n");
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
if (cmd->requesttype & USB_DIR_IN)
|
||
|
stat = dwc_otg_submit_rh_msg_in(dev, buffer, txlen, cmd);
|
||
|
else
|
||
|
stat = dwc_otg_submit_rh_msg_out(dev, buffer, txlen, cmd);
|
||
|
|
||
|
mdelay(1);
|
||
|
|
||
|
return stat;
|
||
|
}
|
||
|
|
||
|
/* U-Boot USB transmission interface */
|
||
|
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
|
||
|
int len)
|
||
|
{
|
||
|
int devnum = usb_pipedevice(pipe);
|
||
|
int ep = usb_pipeendpoint(pipe);
|
||
|
int max = usb_maxpacket(dev, pipe);
|
||
|
int done = 0;
|
||
|
uint32_t hctsiz, sub, tmp;
|
||
|
struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
|
||
|
uint32_t hcint;
|
||
|
uint32_t xfer_len;
|
||
|
uint32_t num_packets;
|
||
|
int stop_transfer = 0;
|
||
|
unsigned int timeout = 1000000;
|
||
|
|
||
|
if (devnum == root_hub_devnum) {
|
||
|
dev->status = 0;
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
if (len > DWC2_DATA_BUF_SIZE) {
|
||
|
printf("%s: %d is more then available buffer size (%d)\n",
|
||
|
__func__, len, DWC2_DATA_BUF_SIZE);
|
||
|
dev->status = 0;
|
||
|
dev->act_len = 0;
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
while ((done < len) && !stop_transfer) {
|
||
|
/* Initialize channel */
|
||
|
dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
|
||
|
usb_pipein(pipe), DWC2_HCCHAR_EPTYPE_BULK, max);
|
||
|
|
||
|
xfer_len = len - done;
|
||
|
/* Make sure that xfer_len is a multiple of max packet size. */
|
||
|
if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
|
||
|
xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
|
||
|
|
||
|
if (xfer_len > 0) {
|
||
|
num_packets = (xfer_len + max - 1) / max;
|
||
|
if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
|
||
|
num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
|
||
|
xfer_len = num_packets * max;
|
||
|
}
|
||
|
} else {
|
||
|
num_packets = 1;
|
||
|
}
|
||
|
|
||
|
if (usb_pipein(pipe))
|
||
|
xfer_len = num_packets * max;
|
||
|
|
||
|
writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
|
||
|
(num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
|
||
|
(bulk_data_toggle[devnum][ep] <<
|
||
|
DWC2_HCTSIZ_PID_OFFSET),
|
||
|
&hc_regs->hctsiz);
|
||
|
|
||
|
memcpy(aligned_buffer, (char *)buffer + done, len - done);
|
||
|
writel((uint32_t)aligned_buffer, &hc_regs->hcdma);
|
||
|
|
||
|
/* Set host channel enable after all other setup is complete. */
|
||
|
clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
|
||
|
DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
|
||
|
(1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
|
||
|
DWC2_HCCHAR_CHEN);
|
||
|
|
||
|
while (1) {
|
||
|
hcint = readl(&hc_regs->hcint);
|
||
|
|
||
|
if (!(hcint & DWC2_HCINT_CHHLTD))
|
||
|
continue;
|
||
|
|
||
|
if (hcint & DWC2_HCINT_XFERCOMP) {
|
||
|
hctsiz = readl(&hc_regs->hctsiz);
|
||
|
done += xfer_len;
|
||
|
|
||
|
sub = hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK;
|
||
|
sub >>= DWC2_HCTSIZ_XFERSIZE_OFFSET;
|
||
|
|
||
|
if (usb_pipein(pipe)) {
|
||
|
done -= sub;
|
||
|
if (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK)
|
||
|
stop_transfer = 1;
|
||
|
}
|
||
|
|
||
|
tmp = hctsiz & DWC2_HCTSIZ_PID_MASK;
|
||
|
tmp >>= DWC2_HCTSIZ_PID_OFFSET;
|
||
|
if (tmp == DWC2_HC_PID_DATA1) {
|
||
|
bulk_data_toggle[devnum][ep] =
|
||
|
DWC2_HC_PID_DATA1;
|
||
|
} else {
|
||
|
bulk_data_toggle[devnum][ep] =
|
||
|
DWC2_HC_PID_DATA0;
|
||
|
}
|
||
|
break;
|
||
|
}
|
||
|
|
||
|
if (hcint & DWC2_HCINT_STALL) {
|
||
|
puts("DWC OTG: Channel halted\n");
|
||
|
bulk_data_toggle[devnum][ep] =
|
||
|
DWC2_HC_PID_DATA0;
|
||
|
|
||
|
stop_transfer = 1;
|
||
|
break;
|
||
|
}
|
||
|
|
||
|
if (!--timeout) {
|
||
|
printf("%s: Timeout!\n", __func__);
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (done && usb_pipein(pipe))
|
||
|
memcpy(buffer, aligned_buffer, done);
|
||
|
|
||
|
writel(0, &hc_regs->hcintmsk);
|
||
|
writel(0xFFFFFFFF, &hc_regs->hcint);
|
||
|
|
||
|
dev->status = 0;
|
||
|
dev->act_len = done;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
|
||
|
int len, struct devrequest *setup)
|
||
|
{
|
||
|
struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
|
||
|
int done = 0;
|
||
|
int devnum = usb_pipedevice(pipe);
|
||
|
int ep = usb_pipeendpoint(pipe);
|
||
|
int max = usb_maxpacket(dev, pipe);
|
||
|
uint32_t hctsiz = 0, sub, tmp, ret;
|
||
|
uint32_t hcint;
|
||
|
const uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP |
|
||
|
DWC2_HCINT_CHHLTD | DWC2_HCINT_ACK;
|
||
|
unsigned int timeout = 1000000;
|
||
|
|
||
|
/* For CONTROL endpoint pid should start with DATA1 */
|
||
|
int status_direction;
|
||
|
|
||
|
if (devnum == root_hub_devnum) {
|
||
|
dev->status = 0;
|
||
|
dev->speed = USB_SPEED_HIGH;
|
||
|
return dwc_otg_submit_rh_msg(dev, pipe, buffer, len, setup);
|
||
|
}
|
||
|
|
||
|
if (len > DWC2_DATA_BUF_SIZE) {
|
||
|
printf("%s: %d is more then available buffer size(%d)\n",
|
||
|
__func__, len, DWC2_DATA_BUF_SIZE);
|
||
|
dev->status = 0;
|
||
|
dev->act_len = 0;
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
/* Initialize channel, OUT for setup buffer */
|
||
|
dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, 0,
|
||
|
DWC2_HCCHAR_EPTYPE_CONTROL, max);
|
||
|
|
||
|
/* SETUP stage */
|
||
|
writel((8 << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
|
||
|
(1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
|
||
|
(DWC2_HC_PID_SETUP << DWC2_HCTSIZ_PID_OFFSET),
|
||
|
&hc_regs->hctsiz);
|
||
|
|
||
|
writel((uint32_t)setup, &hc_regs->hcdma);
|
||
|
|
||
|
/* Set host channel enable after all other setup is complete. */
|
||
|
clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
|
||
|
DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
|
||
|
(1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN);
|
||
|
|
||
|
ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, 1);
|
||
|
if (ret)
|
||
|
printf("%s: Timeout!\n", __func__);
|
||
|
|
||
|
hcint = readl(&hc_regs->hcint);
|
||
|
|
||
|
if (!(hcint & DWC2_HCINT_CHHLTD) || !(hcint & DWC2_HCINT_XFERCOMP)) {
|
||
|
printf("%s: Error (HCINT=%08x)\n", __func__, hcint);
|
||
|
dev->status = 0;
|
||
|
dev->act_len = 0;
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
/* Clear interrupts */
|
||
|
writel(0, &hc_regs->hcintmsk);
|
||
|
writel(0xFFFFFFFF, &hc_regs->hcint);
|
||
|
|
||
|
if (buffer) {
|
||
|
/* DATA stage */
|
||
|
dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
|
||
|
usb_pipein(pipe),
|
||
|
DWC2_HCCHAR_EPTYPE_CONTROL, max);
|
||
|
|
||
|
/* TODO: check if len < 64 */
|
||
|
control_data_toggle[devnum][ep] = DWC2_HC_PID_DATA1;
|
||
|
writel((len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
|
||
|
(1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
|
||
|
(control_data_toggle[devnum][ep] <<
|
||
|
DWC2_HCTSIZ_PID_OFFSET),
|
||
|
&hc_regs->hctsiz);
|
||
|
|
||
|
writel((uint32_t)buffer, &hc_regs->hcdma);
|
||
|
|
||
|
/* Set host channel enable after all other setup is complete */
|
||
|
clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
|
||
|
DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
|
||
|
(1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
|
||
|
DWC2_HCCHAR_CHEN);
|
||
|
|
||
|
while (1) {
|
||
|
hcint = readl(&hc_regs->hcint);
|
||
|
if (!(hcint & DWC2_HCINT_CHHLTD))
|
||
|
continue;
|
||
|
|
||
|
if (hcint & DWC2_HCINT_XFERCOMP) {
|
||
|
hctsiz = readl(&hc_regs->hctsiz);
|
||
|
done = len;
|
||
|
|
||
|
sub = hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK;
|
||
|
sub >>= DWC2_HCTSIZ_XFERSIZE_OFFSET;
|
||
|
|
||
|
if (usb_pipein(pipe))
|
||
|
done -= sub;
|
||
|
}
|
||
|
|
||
|
if (hcint & DWC2_HCINT_ACK) {
|
||
|
tmp = hctsiz & DWC2_HCTSIZ_PID_MASK;
|
||
|
tmp >>= DWC2_HCTSIZ_PID_OFFSET;
|
||
|
if (tmp == DWC2_HC_PID_DATA0) {
|
||
|
control_data_toggle[devnum][ep] =
|
||
|
DWC2_HC_PID_DATA0;
|
||
|
} else {
|
||
|
control_data_toggle[devnum][ep] =
|
||
|
DWC2_HC_PID_DATA1;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (hcint != hcint_comp_hlt_ack) {
|
||
|
printf("%s: Error (HCINT=%08x)\n",
|
||
|
__func__, hcint);
|
||
|
goto out;
|
||
|
}
|
||
|
|
||
|
if (!--timeout) {
|
||
|
printf("%s: Timeout!\n", __func__);
|
||
|
goto out;
|
||
|
}
|
||
|
|
||
|
break;
|
||
|
}
|
||
|
} /* End of DATA stage */
|
||
|
|
||
|
/* STATUS stage */
|
||
|
if ((len == 0) || usb_pipeout(pipe))
|
||
|
status_direction = 1;
|
||
|
else
|
||
|
status_direction = 0;
|
||
|
|
||
|
dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
|
||
|
status_direction, DWC2_HCCHAR_EPTYPE_CONTROL, max);
|
||
|
|
||
|
writel((1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
|
||
|
(DWC2_HC_PID_DATA1 << DWC2_HCTSIZ_PID_OFFSET),
|
||
|
&hc_regs->hctsiz);
|
||
|
|
||
|
writel((uint32_t)status_buffer, &hc_regs->hcdma);
|
||
|
|
||
|
/* Set host channel enable after all other setup is complete. */
|
||
|
clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
|
||
|
DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
|
||
|
(1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN);
|
||
|
|
||
|
while (1) {
|
||
|
hcint = readl(&hc_regs->hcint);
|
||
|
if (hcint & DWC2_HCINT_CHHLTD)
|
||
|
break;
|
||
|
}
|
||
|
|
||
|
if (hcint != hcint_comp_hlt_ack)
|
||
|
printf("%s: Error (HCINT=%08x)\n", __func__, hcint);
|
||
|
|
||
|
out:
|
||
|
dev->act_len = done;
|
||
|
dev->status = 0;
|
||
|
|
||
|
return done;
|
||
|
}
|
||
|
|
||
|
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
|
||
|
int len, int interval)
|
||
|
{
|
||
|
printf("dev = %p pipe = %#lx buf = %p size = %d int = %d\n",
|
||
|
dev, pipe, buffer, len, interval);
|
||
|
return -ENOSYS;
|
||
|
}
|
||
|
|
||
|
/* U-Boot USB control interface */
|
||
|
int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
|
||
|
{
|
||
|
uint32_t snpsid;
|
||
|
int i, j;
|
||
|
|
||
|
root_hub_devnum = 0;
|
||
|
|
||
|
snpsid = readl(®s->gsnpsid);
|
||
|
printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
|
||
|
|
||
|
if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx) {
|
||
|
printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
|
||
|
return -ENODEV;
|
||
|
}
|
||
|
|
||
|
dwc_otg_core_init(regs);
|
||
|
dwc_otg_core_host_init(regs);
|
||
|
|
||
|
clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
|
||
|
DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
|
||
|
DWC2_HPRT0_PRTOVRCURRCHNG,
|
||
|
DWC2_HPRT0_PRTRST);
|
||
|
mdelay(50);
|
||
|
clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
|
||
|
DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
|
||
|
DWC2_HPRT0_PRTRST);
|
||
|
|
||
|
for (i = 0; i < MAX_DEVICE; i++) {
|
||
|
for (j = 0; j < MAX_ENDPOINT; j++) {
|
||
|
control_data_toggle[i][j] = DWC2_HC_PID_DATA1;
|
||
|
bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int usb_lowlevel_stop(int index)
|
||
|
{
|
||
|
/* Put everything in reset. */
|
||
|
clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
|
||
|
DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
|
||
|
DWC2_HPRT0_PRTOVRCURRCHNG,
|
||
|
DWC2_HPRT0_PRTRST);
|
||
|
return 0;
|
||
|
}
|