mirror of
https://github.com/brain-hackers/u-boot-brain
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86 lines
1.8 KiB
C
86 lines
1.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <linux/delay.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8mm_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if IS_ENABLED(CONFIG_FEC_MXC)
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#define FEC_RST_PAD IMX_GPIO_NR(3, 7)
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static iomux_v3_cfg_t const fec1_rst_pads[] = {
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IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
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ARRAY_SIZE(fec1_rst_pads));
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gpio_request(FEC_RST_PAD, "fec1_rst");
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gpio_direction_output(FEC_RST_PAD, 0);
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udelay(500);
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gpio_direction_output(FEC_RST_PAD, 1);
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}
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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setup_iomux_fec();
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/* Use 125M anatop REF_CLK1 for ENET1, not from external */
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clrsetbits_le32(&gpr->gpr[1], 13, 0);
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return set_clk_enet(ENET_125MHZ);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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if (IS_ENABLED(CONFIG_FEC_MXC))
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setup_fec();
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return 0;
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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