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https://github.com/brain-hackers/u-boot-brain
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17 lines
397 B
Plaintext
17 lines
397 B
Plaintext
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gdsys soc bus driver
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This driver provides a simple interface for the busses associated with gdsys
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IHS FPGAs. The bus itself contains devices whose register maps are contained
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within the FPGA's register space.
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Required properties:
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- fpga: A phandle to the controlling IHS FPGA
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Example:
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FPGA0BUS: fpga0bus {
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compatible = "gdsys,soc";
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ranges = <0x0 0xe0600000 0x00004000>;
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fpga = <&FPGA0>;
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};
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