u-boot-brain/arch/arm/mach-sunxi/dram_timings/Makefile

obj-$(CONFIG_SUNXI_DRAM_DDR3_1333)	+= ddr3_1333.o
obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK)	+= lpddr3_stock.o
obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S)	+= ddr2_v3s.o
sunxi: Add selective DRAM type and timing DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> 2017-06-03 18:10:18 +09:00			`obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o`
sunxi: add LPDDR3 timing from stock boot0 As we added LPDDR3 support in the former patch, we need a set of timing info to really enable it. Add the timing info used by stock boot0. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> 2017-06-03 18:10:24 +09:00			`obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o`
sunxi: add support for the DDR2 in V3s SoC Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its timing param. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> 2017-06-03 18:10:20 +09:00			`obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o`