mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-08 13:53:21 +09:00
164 lines
4.5 KiB
C
164 lines
4.5 KiB
C
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/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CFG_POWER_MANAGER
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/memory-map.h>
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#include <asm/arch/platform.h>
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#include "sm.h"
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/* Sanity checks */
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#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
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|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \
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|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
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# error Constraint fCPU >= fHSB >= fPB{A,B} violated
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#endif
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#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
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# error Invalid PLL multiplier and/or divider
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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struct clock_domain_state {
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const struct device *bridge;
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unsigned long freq;
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u32 mask;
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};
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static struct clock_domain_state ckd_state[NR_CLOCK_DOMAINS];
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int pm_enable_clock(enum clock_domain_id id, unsigned int index)
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{
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const struct clock_domain *ckd = &chip_clock[id];
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struct clock_domain_state *state = &ckd_state[id];
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if (ckd->bridge != NO_DEVICE) {
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state->bridge = get_device(ckd->bridge);
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if (!state->bridge)
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return -EBUSY;
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}
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state->mask |= 1 << index;
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if (gd->sm)
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writel(state->mask, gd->sm->regs + ckd->reg);
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return 0;
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}
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void pm_disable_clock(enum clock_domain_id id, unsigned int index)
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{
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const struct clock_domain *ckd = &chip_clock[id];
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struct clock_domain_state *state = &ckd_state[id];
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state->mask &= ~(1 << index);
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if (gd->sm)
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writel(state->mask, gd->sm->regs + ckd->reg);
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if (ckd->bridge)
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put_device(state->bridge);
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}
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unsigned long pm_get_clock_freq(enum clock_domain_id domain)
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{
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return ckd_state[domain].freq;
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}
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void pm_init(void)
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{
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uint32_t cksel = 0;
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unsigned long main_clock;
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/* Make sure we don't disable any device we're already using */
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get_device(DEVICE_HRAMC);
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get_device(DEVICE_HEBI);
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/* Enable the PICO as well */
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ckd_state[CLOCK_CPU].mask |= 1;
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gd->sm = get_device(DEVICE_SM);
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if (!gd->sm)
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panic("Unable to claim system manager device!\n");
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/* Disable any devices that haven't been explicitly claimed */
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sm_writel(gd->sm, PM_PBB_MASK, ckd_state[CLOCK_PBB].mask);
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sm_writel(gd->sm, PM_PBA_MASK, ckd_state[CLOCK_PBA].mask);
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sm_writel(gd->sm, PM_HSB_MASK, ckd_state[CLOCK_HSB].mask);
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sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask);
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#ifdef CONFIG_PLL
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/* Initialize the PLL */
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main_clock = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL;
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sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
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| SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
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| SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
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| SM_BF(PLLOPT, CFG_PLL0_OPT)
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| SM_BF(PLLOSC, 0)
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| SM_BIT(PLLEN)));
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/* Wait for lock */
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while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ;
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#else
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main_clock = CFG_OSC0_HZ;
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#endif
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/* Set up clocks for the CPU and all peripheral buses */
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if (CFG_CLKDIV_CPU) {
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cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
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ckd_state[CLOCK_CPU].freq = main_clock / (1 << CFG_CLKDIV_CPU);
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} else {
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ckd_state[CLOCK_CPU].freq = main_clock;
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}
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if (CFG_CLKDIV_HSB) {
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cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
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ckd_state[CLOCK_HSB].freq = main_clock / (1 << CFG_CLKDIV_HSB);
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} else {
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ckd_state[CLOCK_HSB].freq = main_clock;
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}
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if (CFG_CLKDIV_PBA) {
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cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
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ckd_state[CLOCK_PBA].freq = main_clock / (1 << CFG_CLKDIV_PBA);
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} else {
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ckd_state[CLOCK_PBA].freq = main_clock;
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}
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if (CFG_CLKDIV_PBB) {
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cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
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ckd_state[CLOCK_PBB].freq = main_clock / (1 << CFG_CLKDIV_PBB);
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} else {
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ckd_state[CLOCK_PBB].freq = main_clock;
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}
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sm_writel(gd->sm, PM_CKSEL, cksel);
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/* CFG_HZ currently depends on cpu_hz */
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gd->cpu_hz = ckd_state[CLOCK_CPU].freq;
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#ifdef CONFIG_PLL
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/* Use PLL0 as main clock */
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sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL));
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#endif
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}
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#endif /* CFG_POWER_MANAGER */
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