2017-09-16 04:13:55 +09:00
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/*
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* SuperH Pin Function Controller Support
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*
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* Copyright (c) 2008 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __SH_PFC_H
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#define __SH_PFC_H
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#include <linux/stringify.h>
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enum {
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PINMUX_TYPE_NONE,
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PINMUX_TYPE_FUNCTION,
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PINMUX_TYPE_GPIO,
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PINMUX_TYPE_OUTPUT,
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PINMUX_TYPE_INPUT,
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};
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#define SH_PFC_PIN_CFG_INPUT (1 << 0)
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#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
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#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
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#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
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#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
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#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
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#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
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struct sh_pfc_pin {
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u16 pin;
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u16 enum_id;
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const char *name;
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unsigned int configs;
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};
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2018-06-10 23:05:48 +09:00
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#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
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2017-09-16 04:13:55 +09:00
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{ \
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2018-06-10 23:05:48 +09:00
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.name = #alias, \
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2017-09-16 04:13:55 +09:00
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.pins = n##_pins, \
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.mux = n##_mux, \
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pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
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.nr_pins = ARRAY_SIZE(n##_pins) + \
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BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
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2017-09-16 04:13:55 +09:00
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}
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2018-06-10 23:05:48 +09:00
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#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
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2017-09-16 04:13:55 +09:00
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struct sh_pfc_pin_group {
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const char *name;
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const unsigned int *pins;
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const unsigned int *mux;
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unsigned int nr_pins;
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};
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/*
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2019-03-04 09:32:44 +09:00
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* Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
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* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
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* in this case. It accepts an optional 'version' argument used when the
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* same group can appear on a different set of pins.
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2017-09-16 04:13:55 +09:00
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*/
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2019-03-04 09:32:44 +09:00
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#define VIN_DATA_PIN_GROUP(n, s, ...) \
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{ \
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.name = #n#s#__VA_ARGS__, \
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.pins = n##__VA_ARGS__##_pins.data##s, \
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.mux = n##__VA_ARGS__##_mux.data##s, \
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.nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
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2017-09-16 04:13:55 +09:00
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}
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2019-03-05 06:39:51 +09:00
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union vin_data12 {
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unsigned int data12[12];
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unsigned int data10[10];
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unsigned int data8[8];
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};
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2019-03-04 09:32:44 +09:00
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union vin_data16 {
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unsigned int data16[16];
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unsigned int data12[12];
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unsigned int data10[10];
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unsigned int data8[8];
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};
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2017-09-16 04:13:55 +09:00
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union vin_data {
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unsigned int data24[24];
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unsigned int data20[20];
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unsigned int data16[16];
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unsigned int data12[12];
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unsigned int data10[10];
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unsigned int data8[8];
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unsigned int data4[4];
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};
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#define SH_PFC_FUNCTION(n) \
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{ \
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.name = #n, \
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.groups = n##_groups, \
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.nr_groups = ARRAY_SIZE(n##_groups), \
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}
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struct sh_pfc_function {
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const char *name;
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const char * const *groups;
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unsigned int nr_groups;
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};
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struct pinmux_func {
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u16 enum_id;
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const char *name;
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};
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struct pinmux_cfg_reg {
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u32 reg;
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u8 reg_width, field_width;
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pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
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#ifdef DEBUG
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u16 nr_enum_ids; /* for variable width regs only */
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#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
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#else
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#define SET_NR_ENUM_IDS(n)
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#endif
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2017-09-16 04:13:55 +09:00
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const u16 *enum_ids;
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const u8 *var_field_width;
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};
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pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
|
|
|
#define GROUP(...) __VA_ARGS__
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2017-09-16 04:13:55 +09:00
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/*
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* Describe a config register consisting of several fields of the same width
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* - name: Register name (unused, for documentation purposes only)
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* - r: Physical register address
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* - r_width: Width of the register (in bits)
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* - f_width: Width of the fixed-width register fields (in bits)
|
pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
|
|
|
* - ids: For each register field (from left to right, i.e. MSB to LSB),
|
|
|
|
* 2^f_width enum IDs must be specified, one for each possible
|
|
|
|
* combination of the register field bit values, all wrapped using
|
|
|
|
* the GROUP() macro.
|
2017-09-16 04:13:55 +09:00
|
|
|
*/
|
pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
|
|
|
#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
|
|
|
|
.reg = r, .reg_width = r_width, \
|
|
|
|
.field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
|
|
|
|
BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
|
|
|
|
(r_width / f_width) * (1 << f_width)), \
|
|
|
|
.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
|
|
|
|
{ ids }
|
2017-09-16 04:13:55 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Describe a config register consisting of several fields of different widths
|
|
|
|
* - name: Register name (unused, for documentation purposes only)
|
|
|
|
* - r: Physical register address
|
|
|
|
* - r_width: Width of the register (in bits)
|
pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
|
|
|
* - f_widths: List of widths of the register fields (in bits), from left
|
|
|
|
* to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
|
|
|
|
* - ids: For each register field (from left to right, i.e. MSB to LSB),
|
|
|
|
* 2^f_widths[i] enum IDs must be specified, one for each possible
|
|
|
|
* combination of the register field bit values, all wrapped using
|
|
|
|
* the GROUP() macro.
|
2017-09-16 04:13:55 +09:00
|
|
|
*/
|
pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
|
|
|
#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
|
|
|
|
.reg = r, .reg_width = r_width, \
|
|
|
|
.var_field_width = (const u8 []) { f_widths, 0 }, \
|
|
|
|
SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
|
|
|
|
.enum_ids = (const u16 []) { ids }
|
2017-09-16 04:13:55 +09:00
|
|
|
|
|
|
|
struct pinmux_drive_reg_field {
|
|
|
|
u16 pin;
|
|
|
|
u8 offset;
|
|
|
|
u8 size;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pinmux_drive_reg {
|
|
|
|
u32 reg;
|
|
|
|
const struct pinmux_drive_reg_field fields[8];
|
|
|
|
};
|
|
|
|
|
|
|
|
#define PINMUX_DRIVE_REG(name, r) \
|
|
|
|
.reg = r, \
|
|
|
|
.fields =
|
|
|
|
|
2018-06-10 23:05:48 +09:00
|
|
|
struct pinmux_bias_reg {
|
|
|
|
u32 puen; /* Pull-enable or pull-up control register */
|
|
|
|
u32 pud; /* Pull-up/down control register (optional) */
|
|
|
|
const u16 pins[32];
|
|
|
|
};
|
|
|
|
|
|
|
|
#define PINMUX_BIAS_REG(name1, r1, name2, r2) \
|
|
|
|
.puen = r1, \
|
|
|
|
.pud = r2, \
|
|
|
|
.pins =
|
|
|
|
|
|
|
|
struct pinmux_ioctrl_reg {
|
|
|
|
u32 reg;
|
|
|
|
};
|
|
|
|
|
2017-09-16 04:13:55 +09:00
|
|
|
struct pinmux_data_reg {
|
|
|
|
u32 reg;
|
|
|
|
u8 reg_width;
|
|
|
|
const u16 *enum_ids;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Describe a data register
|
|
|
|
* - name: Register name (unused, for documentation purposes only)
|
|
|
|
* - r: Physical register address
|
|
|
|
* - r_width: Width of the register (in bits)
|
pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
|
|
|
* - ids: For each register bit (from left to right, i.e. MSB to LSB), one
|
|
|
|
* enum ID must be specified, all wrapped using the GROUP() macro.
|
2017-09-16 04:13:55 +09:00
|
|
|
*/
|
pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
|
|
|
#define PINMUX_DATA_REG(name, r, r_width, ids) \
|
|
|
|
.reg = r, .reg_width = r_width + \
|
|
|
|
BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
|
|
|
|
r_width), \
|
|
|
|
.enum_ids = (const u16 [r_width]) { ids }
|
2017-09-16 04:13:55 +09:00
|
|
|
|
|
|
|
struct pinmux_irq {
|
|
|
|
const short *gpios;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Describe the mapping from GPIOs to a single IRQ
|
|
|
|
* - ids...: List of GPIOs that are mapped to the same IRQ
|
|
|
|
*/
|
|
|
|
#define PINMUX_IRQ(ids...) \
|
|
|
|
{ .gpios = (const short []) { ids, -1 } }
|
|
|
|
|
|
|
|
struct pinmux_range {
|
|
|
|
u16 begin;
|
|
|
|
u16 end;
|
|
|
|
u16 force;
|
|
|
|
};
|
|
|
|
|
2018-06-10 23:05:48 +09:00
|
|
|
struct sh_pfc_window {
|
|
|
|
phys_addr_t phys;
|
|
|
|
void __iomem *virt;
|
|
|
|
unsigned long size;
|
2017-09-16 04:13:55 +09:00
|
|
|
};
|
|
|
|
|
|
|
|
struct sh_pfc_pin_range;
|
|
|
|
|
|
|
|
struct sh_pfc {
|
|
|
|
struct device *dev;
|
|
|
|
const struct sh_pfc_soc_info *info;
|
|
|
|
|
|
|
|
void *regs;
|
|
|
|
|
|
|
|
struct sh_pfc_pin_range *ranges;
|
|
|
|
unsigned int nr_ranges;
|
|
|
|
|
|
|
|
unsigned int nr_gpio_pins;
|
|
|
|
|
|
|
|
struct sh_pfc_chip *gpio;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct sh_pfc_soc_operations {
|
|
|
|
int (*init)(struct sh_pfc *pfc);
|
|
|
|
unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
|
|
|
|
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
|
|
|
|
unsigned int bias);
|
|
|
|
int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
|
|
|
|
};
|
|
|
|
|
|
|
|
struct sh_pfc_soc_info {
|
|
|
|
const char *name;
|
|
|
|
const struct sh_pfc_soc_operations *ops;
|
|
|
|
|
|
|
|
struct pinmux_range input;
|
|
|
|
struct pinmux_range output;
|
|
|
|
struct pinmux_range function;
|
|
|
|
|
|
|
|
const struct sh_pfc_pin *pins;
|
|
|
|
unsigned int nr_pins;
|
|
|
|
const struct sh_pfc_pin_group *groups;
|
|
|
|
unsigned int nr_groups;
|
|
|
|
const struct sh_pfc_function *functions;
|
|
|
|
unsigned int nr_functions;
|
|
|
|
|
|
|
|
const struct pinmux_cfg_reg *cfg_regs;
|
|
|
|
const struct pinmux_drive_reg *drive_regs;
|
2018-06-10 23:05:48 +09:00
|
|
|
const struct pinmux_bias_reg *bias_regs;
|
|
|
|
const struct pinmux_ioctrl_reg *ioctrl_regs;
|
2017-09-16 04:13:55 +09:00
|
|
|
const struct pinmux_data_reg *data_regs;
|
|
|
|
|
|
|
|
const u16 *pinmux_data;
|
|
|
|
unsigned int pinmux_data_size;
|
|
|
|
|
|
|
|
const struct pinmux_irq *gpio_irq;
|
|
|
|
unsigned int gpio_irq_size;
|
|
|
|
|
|
|
|
u32 unlock_reg;
|
|
|
|
};
|
|
|
|
|
2018-06-10 23:05:48 +09:00
|
|
|
u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
|
|
|
|
void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
|
|
|
|
const struct pinmux_bias_reg *
|
|
|
|
sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
|
|
|
|
unsigned int *bit);
|
2017-09-16 04:13:55 +09:00
|
|
|
|
2018-01-18 06:18:59 +09:00
|
|
|
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
|
2018-01-18 01:14:45 +09:00
|
|
|
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
|
2018-01-18 06:29:50 +09:00
|
|
|
extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
|
2018-01-18 01:14:45 +09:00
|
|
|
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
|
2018-01-18 06:33:59 +09:00
|
|
|
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
|
2017-09-16 04:13:55 +09:00
|
|
|
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
|
|
|
|
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
|
2019-03-04 09:32:44 +09:00
|
|
|
extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
|
2017-10-10 03:57:29 +09:00
|
|
|
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
|
2018-04-26 20:09:20 +09:00
|
|
|
extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
|
2017-10-09 03:57:37 +09:00
|
|
|
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
2019-03-05 06:39:51 +09:00
|
|
|
|
2017-09-16 04:13:55 +09:00
|
|
|
/* -----------------------------------------------------------------------------
|
|
|
|
* Helper macros to create pin and port lists
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sh_pfc_soc_info pinmux_data array macros
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Describe generic pinmux data
|
|
|
|
* - data_or_mark: *_DATA or *_MARK enum ID
|
|
|
|
* - ids...: List of enum IDs to associate with data_or_mark
|
|
|
|
*/
|
|
|
|
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Describe a pinmux configuration without GPIO function that needs
|
|
|
|
* configuration in a Peripheral Function Select Register (IPSR)
|
|
|
|
* - ipsr: IPSR field (unused, for documentation purposes only)
|
|
|
|
* - fn: Function name, referring to a field in the IPSR
|
|
|
|
*/
|
|
|
|
#define PINMUX_IPSR_NOGP(ipsr, fn) \
|
|
|
|
PINMUX_DATA(fn##_MARK, FN_##fn)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Describe a pinmux configuration with GPIO function that needs configuration
|
|
|
|
* in both a Peripheral Function Select Register (IPSR) and in a
|
|
|
|
* GPIO/Peripheral Function Select Register (GPSR)
|
|
|
|
* - ipsr: IPSR field
|
|
|
|
* - fn: Function name, also referring to the IPSR field
|
|
|
|
*/
|
|
|
|
#define PINMUX_IPSR_GPSR(ipsr, fn) \
|
|
|
|
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Describe a pinmux configuration without GPIO function that needs
|
|
|
|
* configuration in a Peripheral Function Select Register (IPSR), and where the
|
|
|
|
* pinmux function has a representation in a Module Select Register (MOD_SEL).
|
|
|
|
* - ipsr: IPSR field (unused, for documentation purposes only)
|
|
|
|
* - fn: Function name, also referring to the IPSR field
|
|
|
|
* - msel: Module selector
|
|
|
|
*/
|
|
|
|
#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
|
|
|
|
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Describe a pinmux configuration with GPIO function where the pinmux function
|
|
|
|
* has no representation in a Peripheral Function Select Register (IPSR), but
|
|
|
|
* instead solely depends on a group selection.
|
|
|
|
* - gpsr: GPSR field
|
|
|
|
* - fn: Function name, also referring to the GPSR field
|
|
|
|
* - gsel: Group selector
|
|
|
|
*/
|
|
|
|
#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
|
|
|
|
PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Describe a pinmux configuration with GPIO function that needs configuration
|
|
|
|
* in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
|
|
|
|
* Function Select Register (GPSR), and where the pinmux function has a
|
|
|
|
* representation in a Module Select Register (MOD_SEL).
|
|
|
|
* - ipsr: IPSR field
|
|
|
|
* - fn: Function name, also referring to the IPSR field
|
|
|
|
* - msel: Module selector
|
|
|
|
*/
|
|
|
|
#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
|
|
|
|
PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
|
|
|
|
|
2019-03-05 06:39:51 +09:00
|
|
|
/*
|
|
|
|
* Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
|
|
|
|
* an additional select register that controls physical multiplexing
|
|
|
|
* with another pin.
|
|
|
|
* - ipsr: IPSR field
|
|
|
|
* - fn: Function name, also referring to the IPSR field
|
|
|
|
* - psel: Physical multiplexing selector
|
|
|
|
* - msel: Module selector
|
|
|
|
*/
|
|
|
|
#define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
|
|
|
|
PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Describe a pinmux configuration in which a pin is physically multiplexed
|
|
|
|
* with other pins.
|
pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
|
|
|
* - ipsr: IPSR field (unused, for documentation purposes only)
|
|
|
|
* - fn: Function name
|
2019-03-05 06:39:51 +09:00
|
|
|
* - psel: Physical multiplexing selector
|
|
|
|
*/
|
|
|
|
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
|
|
|
|
PINMUX_DATA(fn##_MARK, FN_##psel)
|
|
|
|
|
2017-09-16 04:13:55 +09:00
|
|
|
/*
|
|
|
|
* Describe a pinmux configuration for a single-function pin with GPIO
|
|
|
|
* capability.
|
|
|
|
* - fn: Function name
|
|
|
|
*/
|
|
|
|
#define PINMUX_SINGLE(fn) \
|
|
|
|
PINMUX_DATA(fn##_MARK, FN_##fn)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* GP port style (32 ports banks)
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
|
|
|
|
fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
|
|
|
|
#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
|
|
|
|
|
2017-10-10 03:57:29 +09:00
|
|
|
#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
|
2018-06-10 23:05:48 +09:00
|
|
|
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
|
2017-10-10 03:57:29 +09:00
|
|
|
#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
|
|
|
|
|
2017-09-16 04:13:55 +09:00
|
|
|
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
|
2018-06-10 23:05:48 +09:00
|
|
|
PORT_GP_CFG_6(bank, fn, sfx, cfg), \
|
2017-09-16 04:13:55 +09:00
|
|
|
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_8(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_9(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
|
|
|
|
|
2018-03-07 15:26:12 +09:00
|
|
|
#define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
|
2017-09-16 04:13:55 +09:00
|
|
|
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
|
2019-03-05 06:39:51 +09:00
|
|
|
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
|
2018-03-07 15:26:12 +09:00
|
|
|
#define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
|
2019-03-05 06:39:51 +09:00
|
|
|
PORT_GP_CFG_11(bank, fn, sfx, cfg), \
|
2017-09-16 04:13:55 +09:00
|
|
|
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_12(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_14(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_15(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_16(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_17(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_20(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
|
|
|
|
|
2017-10-10 03:57:29 +09:00
|
|
|
#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
|
2018-06-10 23:05:48 +09:00
|
|
|
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
|
2017-10-10 03:57:29 +09:00
|
|
|
#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
|
|
|
|
|
2017-09-16 04:13:55 +09:00
|
|
|
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
|
2018-06-10 23:05:48 +09:00
|
|
|
PORT_GP_CFG_22(bank, fn, sfx, cfg), \
|
2017-09-16 04:13:55 +09:00
|
|
|
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_23(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
|
|
|
|
|
2018-06-10 23:05:48 +09:00
|
|
|
#define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
|
2017-09-16 04:13:55 +09:00
|
|
|
PORT_GP_CFG_24(bank, fn, sfx, cfg), \
|
2018-06-10 23:05:48 +09:00
|
|
|
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_25(bank, fn, sfx, cfg), \
|
2017-09-16 04:13:55 +09:00
|
|
|
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_26(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_28(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_29(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
|
|
|
|
PORT_GP_CFG_30(bank, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
|
|
|
|
PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
|
|
|
|
#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
|
|
|
|
|
|
|
|
#define PORT_GP_32_REV(bank, fn, sfx) \
|
|
|
|
PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
|
|
|
|
PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
|
|
|
|
|
|
|
|
/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
|
|
|
|
#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
|
|
|
|
#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
|
|
|
|
|
|
|
|
/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
|
|
|
|
#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
|
|
|
|
{ \
|
|
|
|
.pin = (bank * 32) + _pin, \
|
|
|
|
.name = __stringify(_name), \
|
|
|
|
.enum_id = _name##_DATA, \
|
|
|
|
.configs = cfg, \
|
|
|
|
}
|
|
|
|
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
|
|
|
|
|
|
|
|
/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
|
|
|
|
#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
|
|
|
|
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PORT style (linear pin space)
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
|
|
|
|
|
|
|
|
#define PORT_10(pn, fn, pfx, sfx) \
|
|
|
|
PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
|
|
|
|
PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
|
|
|
|
PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
|
|
|
|
PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
|
|
|
|
PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
|
|
|
|
|
|
|
|
#define PORT_90(pn, fn, pfx, sfx) \
|
|
|
|
PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
|
|
|
|
PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
|
|
|
|
PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
|
|
|
|
PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
|
|
|
|
PORT_10(pn+90, fn, pfx##9, sfx)
|
|
|
|
|
|
|
|
/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
|
|
|
|
#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
|
|
|
|
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
|
|
|
|
|
|
|
|
/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
|
|
|
|
#define PINMUX_GPIO(_pin) \
|
|
|
|
[GPIO_##_pin] = { \
|
|
|
|
.pin = (u16)-1, \
|
|
|
|
.name = __stringify(GPIO_##_pin), \
|
|
|
|
.enum_id = _pin##_DATA, \
|
|
|
|
}
|
|
|
|
|
|
|
|
/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
|
|
|
|
#define SH_PFC_PIN_CFG(_pin, cfgs) \
|
|
|
|
{ \
|
|
|
|
.pin = _pin, \
|
|
|
|
.name = __stringify(PORT##_pin), \
|
|
|
|
.enum_id = PORT##_pin##_DATA, \
|
|
|
|
.configs = cfgs, \
|
|
|
|
}
|
|
|
|
|
|
|
|
/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
|
|
|
|
#define SH_PFC_PIN_NAMED(row, col, _name) \
|
|
|
|
{ \
|
|
|
|
.pin = PIN_NUMBER(row, col), \
|
|
|
|
.name = __stringify(PIN_##_name), \
|
|
|
|
.configs = SH_PFC_PIN_CFG_NO_GPIO, \
|
|
|
|
}
|
|
|
|
|
|
|
|
/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
|
|
|
|
#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
|
|
|
|
{ \
|
|
|
|
.pin = PIN_NUMBER(row, col), \
|
|
|
|
.name = __stringify(PIN_##_name), \
|
|
|
|
.configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
|
|
|
|
* PORT_name_OUT, PORT_name_IN marks
|
|
|
|
*/
|
|
|
|
#define _PORT_DATA(pn, pfx, sfx) \
|
|
|
|
PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
|
|
|
|
PORT##pfx##_OUT, PORT##pfx##_IN)
|
|
|
|
#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
|
|
|
|
|
|
|
|
/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
|
|
|
|
#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
|
|
|
|
[gpio - (base)] = { \
|
|
|
|
.name = __stringify(gpio), \
|
|
|
|
.enum_id = data_or_mark, \
|
|
|
|
}
|
|
|
|
#define GPIO_FN(str) \
|
|
|
|
PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PORTnCR helper macro for SH-Mobile/R-Mobile
|
|
|
|
*/
|
|
|
|
#define PORTCR(nr, reg) \
|
|
|
|
{ \
|
pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
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PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
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GROUP(2, 2, 1, 3), \
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GROUP( \
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2017-09-16 04:13:55 +09:00
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/* PULMD[1:0], handled by .set_bias() */ \
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0, 0, 0, 0, \
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/* IE and OE */ \
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0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
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/* SEC, not supported */ \
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0, 0, \
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/* PTMD[2:0] */ \
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PORT##nr##_FN0, PORT##nr##_FN1, \
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PORT##nr##_FN2, PORT##nr##_FN3, \
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PORT##nr##_FN4, PORT##nr##_FN5, \
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PORT##nr##_FN6, PORT##nr##_FN7 \
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pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-10 01:27:11 +09:00
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)) \
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2017-09-16 04:13:55 +09:00
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}
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/*
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* GPIO number helper macro for R-Car
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*/
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#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
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#endif /* __SH_PFC_H */
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