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https://github.com/brain-hackers/u-boot-brain
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394 lines
8.2 KiB
C
394 lines
8.2 KiB
C
![]() |
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2018 NXP
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <asm/arch/sci/sci.h>
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#include <asm/arch/clock.h>
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#include <dt-bindings/clock/imx8qxp-clock.h>
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#include <dt-bindings/soc/imx_rsrc.h>
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#include <misc.h>
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struct imx8_clks {
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ulong id;
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const char *name;
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};
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static struct imx8_clks imx8_clk_names[] = {
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{ IMX8QXP_A35_DIV, "A35_DIV" },
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{ IMX8QXP_I2C0_CLK, "I2C0" },
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{ IMX8QXP_I2C1_CLK, "I2C1" },
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{ IMX8QXP_I2C2_CLK, "I2C2" },
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{ IMX8QXP_I2C3_CLK, "I2C3" },
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{ IMX8QXP_UART0_CLK, "UART0" },
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{ IMX8QXP_UART1_CLK, "UART1" },
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{ IMX8QXP_UART2_CLK, "UART2" },
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{ IMX8QXP_UART3_CLK, "UART3" },
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{ IMX8QXP_SDHC0_CLK, "SDHC0" },
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{ IMX8QXP_SDHC1_CLK, "SDHC1" },
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{ IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" },
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{ IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" },
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{ IMX8QXP_ENET0_REF_DIV, "ENET0_REF" },
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{ IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" },
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{ IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" },
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{ IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" },
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{ IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
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{ IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
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};
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static ulong imx8_clk_get_rate(struct clk *clk)
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{
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sc_pm_clk_t pm_clk;
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ulong rate;
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u16 resource;
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int ret;
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debug("%s(#%lu)\n", __func__, clk->id);
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switch (clk->id) {
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case IMX8QXP_A35_DIV:
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resource = SC_R_A35;
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pm_clk = SC_PM_CLK_CPU;
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break;
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case IMX8QXP_I2C0_CLK:
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resource = SC_R_I2C_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_I2C1_CLK:
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resource = SC_R_I2C_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_I2C2_CLK:
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resource = SC_R_I2C_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_I2C3_CLK:
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resource = SC_R_I2C_3;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_SDHC0_IPG_CLK:
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case IMX8QXP_SDHC0_CLK:
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case IMX8QXP_SDHC0_DIV:
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resource = SC_R_SDHC_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_SDHC1_IPG_CLK:
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case IMX8QXP_SDHC1_CLK:
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case IMX8QXP_SDHC1_DIV:
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resource = SC_R_SDHC_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART0_IPG_CLK:
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case IMX8QXP_UART0_CLK:
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resource = SC_R_UART_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART1_CLK:
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resource = SC_R_UART_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART2_CLK:
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resource = SC_R_UART_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART3_CLK:
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resource = SC_R_UART_3;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_ENET0_IPG_CLK:
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case IMX8QXP_ENET0_AHB_CLK:
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case IMX8QXP_ENET0_REF_DIV:
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case IMX8QXP_ENET0_PTP_CLK:
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resource = SC_R_ENET_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_ENET1_IPG_CLK:
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case IMX8QXP_ENET1_AHB_CLK:
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case IMX8QXP_ENET1_REF_DIV:
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case IMX8QXP_ENET1_PTP_CLK:
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resource = SC_R_ENET_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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default:
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if (clk->id < IMX8QXP_UART0_IPG_CLK ||
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clk->id >= IMX8QXP_CLK_END) {
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printf("%s(Invalid clk ID #%lu)\n",
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__func__, clk->id);
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return -EINVAL;
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}
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return -ENOTSUPP;
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};
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ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
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(sc_pm_clock_rate_t *)&rate);
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if (ret) {
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printf("%s err %d\n", __func__, ret);
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return ret;
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}
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return rate;
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}
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static ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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sc_pm_clk_t pm_clk;
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u32 new_rate = rate;
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u16 resource;
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int ret;
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debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
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switch (clk->id) {
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case IMX8QXP_I2C0_CLK:
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resource = SC_R_I2C_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_I2C1_CLK:
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resource = SC_R_I2C_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_I2C2_CLK:
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resource = SC_R_I2C_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_I2C3_CLK:
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resource = SC_R_I2C_3;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART0_CLK:
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resource = SC_R_UART_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART1_CLK:
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resource = SC_R_UART_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART2_CLK:
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resource = SC_R_UART_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART3_CLK:
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resource = SC_R_UART_3;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_SDHC0_IPG_CLK:
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case IMX8QXP_SDHC0_CLK:
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case IMX8QXP_SDHC0_DIV:
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resource = SC_R_SDHC_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_SDHC1_SEL:
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case IMX8QXP_SDHC0_SEL:
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return 0;
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case IMX8QXP_SDHC1_IPG_CLK:
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case IMX8QXP_SDHC1_CLK:
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case IMX8QXP_SDHC1_DIV:
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resource = SC_R_SDHC_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_ENET0_IPG_CLK:
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case IMX8QXP_ENET0_AHB_CLK:
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case IMX8QXP_ENET0_REF_DIV:
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case IMX8QXP_ENET0_PTP_CLK:
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resource = SC_R_ENET_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_ENET1_IPG_CLK:
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case IMX8QXP_ENET1_AHB_CLK:
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case IMX8QXP_ENET1_REF_DIV:
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case IMX8QXP_ENET1_PTP_CLK:
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resource = SC_R_ENET_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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default:
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if (clk->id < IMX8QXP_UART0_IPG_CLK ||
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clk->id >= IMX8QXP_CLK_END) {
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printf("%s(Invalid clk ID #%lu)\n",
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__func__, clk->id);
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return -EINVAL;
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}
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return -ENOTSUPP;
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};
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ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
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if (ret) {
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printf("%s err %d\n", __func__, ret);
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return ret;
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}
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return new_rate;
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}
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static int __imx8_clk_enable(struct clk *clk, bool enable)
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{
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sc_pm_clk_t pm_clk;
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u16 resource;
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int ret;
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debug("%s(#%lu)\n", __func__, clk->id);
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switch (clk->id) {
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case IMX8QXP_I2C0_CLK:
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resource = SC_R_I2C_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_I2C1_CLK:
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resource = SC_R_I2C_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_I2C2_CLK:
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resource = SC_R_I2C_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_I2C3_CLK:
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resource = SC_R_I2C_3;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART0_CLK:
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resource = SC_R_UART_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART1_CLK:
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resource = SC_R_UART_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART2_CLK:
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resource = SC_R_UART_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_UART3_CLK:
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resource = SC_R_UART_3;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_SDHC0_IPG_CLK:
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case IMX8QXP_SDHC0_CLK:
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case IMX8QXP_SDHC0_DIV:
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resource = SC_R_SDHC_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_SDHC1_IPG_CLK:
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case IMX8QXP_SDHC1_CLK:
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case IMX8QXP_SDHC1_DIV:
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resource = SC_R_SDHC_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_ENET0_IPG_CLK:
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case IMX8QXP_ENET0_AHB_CLK:
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case IMX8QXP_ENET0_REF_DIV:
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case IMX8QXP_ENET0_PTP_CLK:
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resource = SC_R_ENET_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QXP_ENET1_IPG_CLK:
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case IMX8QXP_ENET1_AHB_CLK:
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case IMX8QXP_ENET1_REF_DIV:
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case IMX8QXP_ENET1_PTP_CLK:
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resource = SC_R_ENET_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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default:
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if (clk->id < IMX8QXP_UART0_IPG_CLK ||
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clk->id >= IMX8QXP_CLK_END) {
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printf("%s(Invalid clk ID #%lu)\n",
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__func__, clk->id);
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return -EINVAL;
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}
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return -ENOTSUPP;
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}
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ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
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if (ret) {
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printf("%s err %d\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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static int imx8_clk_disable(struct clk *clk)
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{
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return __imx8_clk_enable(clk, 0);
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}
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static int imx8_clk_enable(struct clk *clk)
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{
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return __imx8_clk_enable(clk, 1);
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}
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#if CONFIG_IS_ENABLED(CMD_CLK)
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int soc_clk_dump(void)
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{
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struct udevice *dev;
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struct clk clk;
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unsigned long rate;
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int i, ret;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(imx8_clk), &dev);
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if (ret)
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return ret;
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printf("Clk\t\tHz\n");
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for (i = 0; i < ARRAY_SIZE(imx8_clk_names); i++) {
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clk.id = imx8_clk_names[i].id;
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ret = clk_request(dev, &clk);
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if (ret < 0) {
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debug("%s clk_request() failed: %d\n", __func__, ret);
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continue;
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}
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ret = clk_get_rate(&clk);
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rate = ret;
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clk_free(&clk);
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if (ret == -ENOTSUPP) {
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printf("clk ID %lu not supported yet\n",
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imx8_clk_names[i].id);
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continue;
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}
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if (ret < 0) {
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printf("%s %lu: get_rate err: %d\n",
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__func__, imx8_clk_names[i].id, ret);
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continue;
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}
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printf("%s(%3lu):\t%lu\n",
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imx8_clk_names[i].name, imx8_clk_names[i].id, rate);
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}
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return 0;
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}
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#endif
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static struct clk_ops imx8_clk_ops = {
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.set_rate = imx8_clk_set_rate,
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.get_rate = imx8_clk_get_rate,
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.enable = imx8_clk_enable,
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.disable = imx8_clk_disable,
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};
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static int imx8_clk_probe(struct udevice *dev)
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{
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return 0;
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}
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static const struct udevice_id imx8_clk_ids[] = {
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{ .compatible = "fsl,imx8qxp-clk" },
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{ },
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};
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U_BOOT_DRIVER(imx8_clk) = {
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.name = "clk_imx8",
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.id = UCLASS_CLK,
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.of_match = imx8_clk_ids,
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.ops = &imx8_clk_ops,
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.probe = imx8_clk_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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