u-boot-brain/board/inka4x0/mt46v32m16-75.h

/*
 * Copyright (C) 2007 Semihalf
 * Written by Marian Balakowicz <m8@semihalf.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#define SDRAM_DDR	1		/* is DDR */

/* Settings for XLB = 132 MHz */
#define SDRAM_MODE	0x018D0000
#define SDRAM_EMODE	0x40090000
#define SDRAM_CONTROL	0x714F0F00
#define SDRAM_CONFIG1	0x73711930
#define SDRAM_CONFIG2	0x46770000
#define SDRAM_TAPDELAY	0x10000000
[INKA4x0] NG hardware: SDRAM support Add support for three new DDR chips that may be present on a NG INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT. Cleanup board/inka4x0/mt48lc16m16a2-75.h file. Signed-off-by: Marian Balakowicz <m8@semihalf.com> 2007-11-15 21:29:55 +09:00			`/*`
			`* Copyright (C) 2007 Semihalf`
			`* Written by Marian Balakowicz <m8@semihalf.com>`
			`*`
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> 2013-07-08 16:37:19 +09:00			`* SPDX-License-Identifier: GPL-2.0+`
[INKA4x0] NG hardware: SDRAM support Add support for three new DDR chips that may be present on a NG INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT. Cleanup board/inka4x0/mt48lc16m16a2-75.h file. Signed-off-by: Marian Balakowicz <m8@semihalf.com> 2007-11-15 21:29:55 +09:00			`*/`

			`#define SDRAM_DDR 1 /* is DDR */`

			`/* Settings for XLB = 132 MHz */`
			`#define SDRAM_MODE 0x018D0000`
			`#define SDRAM_EMODE 0x40090000`
			`#define SDRAM_CONTROL 0x714F0F00`
			`#define SDRAM_CONFIG1 0x73711930`
			`#define SDRAM_CONFIG2 0x46770000`
			`#define SDRAM_TAPDELAY 0x10000000`