u-boot-brain/board/freescale/b4860qds/b4_rcw.cfg

#PBL preamble and RCW header
aa55aa55 010e0100
# serdes protocol 0x2A_0x98
140e0018 0f001218 00000000 00000000
54980000 9000a000 e8104000 a9000000
01000000 00000000 00000000 0001b1f8
00000000 14000020 00000000 00000011
powerpc/B4860: enable PBL tool for B4860 Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> 2013-09-22 10:56:02 +09:00			`#PBL preamble and RCW header`
			`aa55aa55 010e0100`
			`# serdes protocol 0x2A_0x98`
			`140e0018 0f001218 00000000 00000000`
powerpc/b4860/pbl: fix rcw cfg The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> 2013-12-19 14:38:11 +09:00			`54980000 9000a000 e8104000 a9000000`
powerpc/B4860: enable PBL tool for B4860 Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> 2013-09-22 10:56:02 +09:00			`01000000 00000000 00000000 0001b1f8`
			`00000000 14000020 00000000 00000011`