mirror of
https://github.com/brain-hackers/u-boot-brain
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281 lines
6.8 KiB
C
281 lines
6.8 KiB
C
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/*
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* (C) Copyright 2013 Inc.
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*
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* Xilinx Zynq PS SPI controller driver (master mode only)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
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#define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */
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#define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */
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#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */
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#define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */
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#define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */
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#define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */
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#define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */
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#define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */
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#define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */
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#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */
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#define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */
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#define ZYNQ_SPI_FIFO_DEPTH 128
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#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
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#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
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#endif
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/* zynq spi register set */
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struct zynq_spi_regs {
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u32 cr; /* 0x00 */
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u32 isr; /* 0x04 */
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u32 ier; /* 0x08 */
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u32 idr; /* 0x0C */
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u32 imr; /* 0x10 */
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u32 enr; /* 0x14 */
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u32 dr; /* 0x18 */
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u32 txdr; /* 0x1C */
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u32 rxdr; /* 0x20 */
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};
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/* zynq spi slave */
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struct zynq_spi_slave {
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struct spi_slave slave;
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struct zynq_spi_regs *base;
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u8 mode;
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u8 fifo_depth;
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u32 speed_hz;
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u32 input_hz;
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u32 req_hz;
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};
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static inline struct zynq_spi_slave *to_zynq_spi_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct zynq_spi_slave, slave);
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}
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static inline struct zynq_spi_regs *get_zynq_spi_base(int dev)
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{
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if (dev)
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return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
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else
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return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
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}
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static void zynq_spi_init_hw(struct zynq_spi_slave *zslave)
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{
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u32 confr;
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/* Disable SPI */
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writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
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/* Disable Interrupts */
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writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->idr);
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/* Clear RX FIFO */
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while (readl(&zslave->base->isr) &
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ZYNQ_SPI_IXR_RXNEMPTY_MASK)
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readl(&zslave->base->rxdr);
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/* Clear Interrupts */
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writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->isr);
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/* Manual slave select and Auto start */
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confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
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ZYNQ_SPI_CR_MSTREN_MASK;
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confr &= ~ZYNQ_SPI_CR_MSA_MASK;
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writel(confr, &zslave->base->cr);
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/* Enable SPI */
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writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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/* 2 bus with 3 chipselect */
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return bus < 2 && cs < 3;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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u32 cr;
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debug("spi_cs_activate: 0x%08x\n", (u32)slave);
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clrbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK);
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cr = readl(&zslave->base->cr);
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/*
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* CS cal logic: CS[13:10]
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* xxx0 - cs0
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* xx01 - cs1
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* x011 - cs2
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*/
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cr |= (~(0x1 << slave->cs) << 10) & ZYNQ_SPI_CR_CS_MASK;
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writel(cr, &zslave->base->cr);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
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setbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK);
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}
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void spi_init()
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{
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/* nothing to do */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct zynq_spi_slave *zslave;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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zslave = spi_alloc_slave(struct zynq_spi_slave, bus, cs);
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if (!zslave) {
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printf("SPI_error: Fail to allocate zynq_spi_slave\n");
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return NULL;
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}
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zslave->base = get_zynq_spi_base(bus);
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zslave->mode = mode;
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zslave->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
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zslave->input_hz = 166666700;
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zslave->speed_hz = zslave->input_hz / 2;
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zslave->req_hz = max_hz;
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/* init the zynq spi hw */
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zynq_spi_init_hw(zslave);
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return &zslave->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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debug("spi_free_slave: 0x%08x\n", (u32)slave);
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free(zslave);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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u32 confr = 0;
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u8 baud_rate_val = 0;
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writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
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/* Set the SPI Clock phase and polarities */
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confr = readl(&zslave->base->cr);
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confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
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if (zslave->mode & SPI_CPHA)
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confr |= ZYNQ_SPI_CR_CPHA_MASK;
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if (zslave->mode & SPI_CPOL)
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confr |= ZYNQ_SPI_CR_CPOL_MASK;
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/* Set the clock frequency */
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if (zslave->req_hz == 0) {
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/* Set baudrate x8, if the req_hz is 0 */
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baud_rate_val = 0x2;
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} else if (zslave->speed_hz != zslave->req_hz) {
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while ((baud_rate_val < 8) &&
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((zslave->input_hz /
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(2 << baud_rate_val)) > zslave->req_hz))
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baud_rate_val++;
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zslave->speed_hz = zslave->req_hz / (2 << baud_rate_val);
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}
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confr &= ~ZYNQ_SPI_CR_BRD_MASK;
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confr |= (baud_rate_val << 3);
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writel(confr, &zslave->base->cr);
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writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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debug("spi_release_bus: 0x%08x\n", (u32)slave);
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writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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u32 len = bitlen / 8;
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u32 tx_len = len, rx_len = len, tx_tvl;
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const u8 *tx_buf = dout;
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u8 *rx_buf = din, buf;
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u32 ts, status;
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debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
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slave->bus, slave->cs, bitlen, len, flags);
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if (bitlen == 0)
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return -1;
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if (bitlen % 8) {
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debug("spi_xfer: Non byte aligned SPI transfer\n");
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return -1;
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}
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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while (rx_len > 0) {
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/* Write the data into TX FIFO - tx threshold is fifo_depth */
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tx_tvl = 0;
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while ((tx_tvl < zslave->fifo_depth) && tx_len) {
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if (tx_buf)
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buf = *tx_buf++;
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else
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buf = 0;
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writel(buf, &zslave->base->txdr);
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tx_len--;
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tx_tvl++;
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}
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/* Check TX FIFO completion */
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ts = get_timer(0);
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status = readl(&zslave->base->isr);
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while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
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if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
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printf("spi_xfer: Timeout! TX FIFO not full\n");
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return -1;
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}
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status = readl(&zslave->base->isr);
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}
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/* Read the data from RX FIFO */
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status = readl(&zslave->base->isr);
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while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) {
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buf = readl(&zslave->base->rxdr);
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if (rx_buf)
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*rx_buf++ = buf;
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status = readl(&zslave->base->isr);
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rx_len--;
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}
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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return 0;
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}
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