mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-02 19:03:20 +09:00
483 lines
13 KiB
C
483 lines
13 KiB
C
![]() |
/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*
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* Freescale Quad Serial Peripheral Interface (QSPI) driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include "fsl_qspi.h"
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#define RX_BUFFER_SIZE 0x80
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#define TX_BUFFER_SIZE 0x40
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#define OFFSET_BITS_MASK 0x00ffffff
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#define FLASH_STATUS_WEL 0x02
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/* SEQID */
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#define SEQID_WREN 1
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#define SEQID_FAST_READ 2
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#define SEQID_RDSR 3
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#define SEQID_SE 4
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#define SEQID_CHIP_ERASE 5
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#define SEQID_PP 6
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#define SEQID_RDID 7
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/* Flash opcodes */
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#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
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#define OPCODE_RDSR 0x05 /* Read status register */
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#define OPCODE_WREN 0x06 /* Write enable */
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#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
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#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
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#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
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#define OPCODE_RDID 0x9f /* Read JEDEC ID */
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/* 4-byte address opcodes - used on Spansion and some Macronix flashes */
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#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
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#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
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#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
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#ifdef CONFIG_SYS_FSL_QSPI_LE
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#define qspi_read32 in_le32
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#define qspi_write32 out_le32
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#elif defined(CONFIG_SYS_FSL_QSPI_BE)
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#define qspi_read32 in_be32
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#define qspi_write32 out_be32
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#endif
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static unsigned long spi_bases[] = {
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QSPI0_BASE_ADDR,
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};
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static unsigned long amba_bases[] = {
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QSPI0_AMBA_BASE,
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};
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struct fsl_qspi {
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struct spi_slave slave;
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unsigned long reg_base;
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unsigned long amba_base;
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u32 sf_addr;
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u8 cur_seqid;
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};
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/* QSPI support swapping the flash read/write data
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* in hardware for LS102xA, but not for VF610 */
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static inline u32 qspi_endian_xchg(u32 data)
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{
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#ifdef CONFIG_VF610
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return swab32(data);
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#else
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return data;
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#endif
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}
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static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct fsl_qspi, slave);
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}
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static void qspi_set_lut(struct fsl_qspi *qspi)
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{
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struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
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u32 lut_base;
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/* Unlock the LUT */
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qspi_write32(®s->lutkey, LUT_KEY_VALUE);
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qspi_write32(®s->lckcr, QSPI_LCKCR_UNLOCK);
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/* Write Enable */
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lut_base = SEQID_WREN * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_WREN) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
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qspi_write32(®s->lut[lut_base + 1], 0);
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qspi_write32(®s->lut[lut_base + 2], 0);
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qspi_write32(®s->lut[lut_base + 3], 0);
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/* Fast Read */
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lut_base = SEQID_FAST_READ * 4;
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if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_FAST_READ) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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else
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_FAST_READ_4B) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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qspi_write32(®s->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) |
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INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
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INSTR1(LUT_READ));
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qspi_write32(®s->lut[lut_base + 2], 0);
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qspi_write32(®s->lut[lut_base + 3], 0);
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/* Read Status */
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lut_base = SEQID_RDSR * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_RDSR) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
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PAD1(LUT_PAD1) | INSTR1(LUT_READ));
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qspi_write32(®s->lut[lut_base + 1], 0);
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qspi_write32(®s->lut[lut_base + 2], 0);
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qspi_write32(®s->lut[lut_base + 3], 0);
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/* Erase a sector */
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lut_base = SEQID_SE * 4;
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if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_SE) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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else
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_SE_4B) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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qspi_write32(®s->lut[lut_base + 1], 0);
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qspi_write32(®s->lut[lut_base + 2], 0);
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qspi_write32(®s->lut[lut_base + 3], 0);
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/* Erase the whole chip */
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lut_base = SEQID_CHIP_ERASE * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_CHIP_ERASE) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
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qspi_write32(®s->lut[lut_base + 1], 0);
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qspi_write32(®s->lut[lut_base + 2], 0);
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qspi_write32(®s->lut[lut_base + 3], 0);
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/* Page Program */
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lut_base = SEQID_PP * 4;
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if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_PP) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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else
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_PP_4B) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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qspi_write32(®s->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
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PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
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qspi_write32(®s->lut[lut_base + 2], 0);
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qspi_write32(®s->lut[lut_base + 3], 0);
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/* READ ID */
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lut_base = SEQID_RDID * 4;
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qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_RDID) |
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PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
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PAD1(LUT_PAD1) | INSTR1(LUT_READ));
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qspi_write32(®s->lut[lut_base + 1], 0);
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qspi_write32(®s->lut[lut_base + 2], 0);
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qspi_write32(®s->lut[lut_base + 3], 0);
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/* Lock the LUT */
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qspi_write32(®s->lutkey, LUT_KEY_VALUE);
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qspi_write32(®s->lckcr, QSPI_LCKCR_LOCK);
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}
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void spi_init()
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{
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/* do nothing */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct fsl_qspi *qspi;
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struct fsl_qspi_regs *regs;
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u32 reg_val, smpr_val;
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u32 total_size, seq_id;
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if (bus >= ARRAY_SIZE(spi_bases))
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return NULL;
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qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
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if (!qspi)
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return NULL;
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qspi->reg_base = spi_bases[bus];
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qspi->amba_base = amba_bases[bus];
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qspi->slave.max_write_size = TX_BUFFER_SIZE;
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regs = (struct fsl_qspi_regs *)qspi->reg_base;
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qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
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smpr_val = qspi_read32(®s->smpr);
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qspi_write32(®s->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK |
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QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK));
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qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK);
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total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
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qspi_write32(®s->sfa1ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base);
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qspi_write32(®s->sfa2ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base);
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qspi_write32(®s->sfb1ad, total_size | qspi->amba_base);
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qspi_write32(®s->sfb2ad, total_size | qspi->amba_base);
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qspi_set_lut(qspi);
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smpr_val = qspi_read32(®s->smpr);
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smpr_val &= ~QSPI_SMPR_DDRSMP_MASK;
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qspi_write32(®s->smpr, smpr_val);
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qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK);
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seq_id = 0;
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reg_val = qspi_read32(®s->bfgencr);
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reg_val &= ~QSPI_BFGENCR_SEQID_MASK;
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reg_val |= (seq_id << QSPI_BFGENCR_SEQID_SHIFT);
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reg_val &= ~QSPI_BFGENCR_PAR_EN_MASK;
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qspi_write32(®s->bfgencr, reg_val);
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return &qspi->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct fsl_qspi *qspi = to_qspi_spi(slave);
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free(qspi);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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return 0;
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}
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static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
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{
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struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
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u32 mcr_reg, rbsr_reg, data;
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int i, size;
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mcr_reg = qspi_read32(®s->mcr);
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qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
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QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
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qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
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qspi_write32(®s->sfar, qspi->amba_base);
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qspi_write32(®s->ipcr, (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
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while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
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;
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i = 0;
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size = len;
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while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
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rbsr_reg = qspi_read32(®s->rbsr);
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if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
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data = qspi_read32(®s->rbdr[i]);
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data = qspi_endian_xchg(data);
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memcpy(rxbuf, &data, 4);
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rxbuf++;
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size -= 4;
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i++;
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}
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}
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qspi_write32(®s->mcr, mcr_reg);
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}
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static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
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{
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struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
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u32 mcr_reg, data;
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int i, size;
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u32 to_or_from;
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mcr_reg = qspi_read32(®s->mcr);
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qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
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QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
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qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
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to_or_from = qspi->sf_addr + qspi->amba_base;
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while (len > 0) {
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qspi_write32(®s->sfar, to_or_from);
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size = (len > RX_BUFFER_SIZE) ?
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RX_BUFFER_SIZE : len;
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qspi_write32(®s->ipcr,
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(SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) | size);
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while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
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;
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to_or_from += size;
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len -= size;
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i = 0;
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while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
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data = qspi_read32(®s->rbdr[i]);
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data = qspi_endian_xchg(data);
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memcpy(rxbuf, &data, 4);
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rxbuf++;
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size -= 4;
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i++;
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}
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qspi_write32(®s->mcr, qspi_read32(®s->mcr) |
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QSPI_MCR_CLR_RXF_MASK);
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}
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qspi_write32(®s->mcr, mcr_reg);
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}
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static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf, u32 len)
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{
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struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
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u32 mcr_reg, data, reg, status_reg;
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int i, size, tx_size;
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u32 to_or_from = 0;
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mcr_reg = qspi_read32(®s->mcr);
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qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
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QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
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qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
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status_reg = 0;
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while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
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qspi_write32(®s->ipcr,
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(SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
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while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
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;
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qspi_write32(®s->ipcr,
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(SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
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while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
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;
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reg = qspi_read32(®s->rbsr);
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if (reg & QSPI_RBSR_RDBFL_MASK) {
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status_reg = qspi_read32(®s->rbdr[0]);
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status_reg = qspi_endian_xchg(status_reg);
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}
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qspi_write32(®s->mcr,
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qspi_read32(®s->mcr) | QSPI_MCR_CLR_RXF_MASK);
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}
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to_or_from = qspi->sf_addr + qspi->amba_base;
|
||
|
qspi_write32(®s->sfar, to_or_from);
|
||
|
|
||
|
tx_size = (len > TX_BUFFER_SIZE) ?
|
||
|
TX_BUFFER_SIZE : len;
|
||
|
|
||
|
size = (tx_size + 3) / 4;
|
||
|
|
||
|
for (i = 0; i < size; i++) {
|
||
|
data = qspi_endian_xchg(*txbuf);
|
||
|
qspi_write32(®s->tbdr, data);
|
||
|
txbuf++;
|
||
|
}
|
||
|
|
||
|
qspi_write32(®s->ipcr,
|
||
|
(SEQID_PP << QSPI_IPCR_SEQID_SHIFT) | tx_size);
|
||
|
while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
|
||
|
;
|
||
|
|
||
|
qspi_write32(®s->mcr, mcr_reg);
|
||
|
}
|
||
|
|
||
|
static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf)
|
||
|
{
|
||
|
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
|
||
|
u32 mcr_reg, reg, data;
|
||
|
|
||
|
mcr_reg = qspi_read32(®s->mcr);
|
||
|
qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
|
||
|
QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
|
||
|
qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
|
||
|
|
||
|
qspi_write32(®s->sfar, qspi->amba_base);
|
||
|
|
||
|
qspi_write32(®s->ipcr,
|
||
|
(SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
|
||
|
while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
|
||
|
;
|
||
|
|
||
|
while (1) {
|
||
|
reg = qspi_read32(®s->rbsr);
|
||
|
if (reg & QSPI_RBSR_RDBFL_MASK) {
|
||
|
data = qspi_read32(®s->rbdr[0]);
|
||
|
data = qspi_endian_xchg(data);
|
||
|
memcpy(rxbuf, &data, 4);
|
||
|
qspi_write32(®s->mcr, qspi_read32(®s->mcr) |
|
||
|
QSPI_MCR_CLR_RXF_MASK);
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
qspi_write32(®s->mcr, mcr_reg);
|
||
|
}
|
||
|
|
||
|
static void qspi_op_se(struct fsl_qspi *qspi)
|
||
|
{
|
||
|
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
|
||
|
u32 mcr_reg;
|
||
|
u32 to_or_from = 0;
|
||
|
|
||
|
mcr_reg = qspi_read32(®s->mcr);
|
||
|
qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
|
||
|
QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
|
||
|
qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
|
||
|
|
||
|
to_or_from = qspi->sf_addr + qspi->amba_base;
|
||
|
qspi_write32(®s->sfar, to_or_from);
|
||
|
|
||
|
qspi_write32(®s->ipcr,
|
||
|
(SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
|
||
|
while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
|
||
|
;
|
||
|
|
||
|
qspi_write32(®s->ipcr,
|
||
|
(SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
|
||
|
while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
|
||
|
;
|
||
|
|
||
|
qspi_write32(®s->mcr, mcr_reg);
|
||
|
}
|
||
|
|
||
|
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||
|
const void *dout, void *din, unsigned long flags)
|
||
|
{
|
||
|
struct fsl_qspi *qspi = to_qspi_spi(slave);
|
||
|
u32 bytes = DIV_ROUND_UP(bitlen, 8);
|
||
|
static u32 pp_sfaddr;
|
||
|
u32 txbuf;
|
||
|
|
||
|
if (dout) {
|
||
|
memcpy(&txbuf, dout, 4);
|
||
|
qspi->cur_seqid = *(u8 *)dout;
|
||
|
|
||
|
if (flags == SPI_XFER_END) {
|
||
|
qspi->sf_addr = pp_sfaddr;
|
||
|
qspi_op_pp(qspi, (u32 *)dout, bytes);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
if (qspi->cur_seqid == OPCODE_FAST_READ) {
|
||
|
qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
|
||
|
} else if (qspi->cur_seqid == OPCODE_SE) {
|
||
|
qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
|
||
|
qspi_op_se(qspi);
|
||
|
} else if (qspi->cur_seqid == OPCODE_PP) {
|
||
|
pp_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (din) {
|
||
|
if (qspi->cur_seqid == OPCODE_FAST_READ)
|
||
|
qspi_op_read(qspi, din, bytes);
|
||
|
else if (qspi->cur_seqid == OPCODE_RDID)
|
||
|
qspi_op_rdid(qspi, din, bytes);
|
||
|
else if (qspi->cur_seqid == OPCODE_RDSR)
|
||
|
qspi_op_rdsr(qspi, din);
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
void spi_release_bus(struct spi_slave *slave)
|
||
|
{
|
||
|
/* Nothing to do */
|
||
|
}
|