2012-12-11 22:34:13 +09:00
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/*
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2014-01-25 02:37:36 +09:00
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* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
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2012-12-11 22:34:13 +09:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/flow.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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#include "../tegra-common/cpu.h"
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/* Tegra30-specific CPU init code */
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void tegra_i2c_ll_write_addr(uint addr, uint config)
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{
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struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
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writel(addr, ®->cmd_addr0);
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writel(config, ®->cnfg);
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}
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void tegra_i2c_ll_write_data(uint data, uint config)
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{
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struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
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writel(data, ®->cmd_data1);
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writel(config, ®->cnfg);
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}
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ARM: tegra: use a CPU freq that all SKUs can support
U-Boot on Tegra30 currently selects a main CPU frequency that cannot be
supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values
on some others. This can result in unreliable operation of the main CPUs.
Resolve this by switching to a CPU frequency that can be supported by any
SKU. According to the following link, the maximum supported CPU frequency
of the slowest Tegra30 SKU is 600MHz:
repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary
branch l4t/l4t-r16-r2
path arch/arm/mach-tegra/tegra3_dvfs.c
table cpu_dvfs_table[]
According to that same table, the minimum VDD_CPU required to operate at
that frequency across all SKUs is 1.007V. Given the adjustment resolution
of the TPS65911 PMIC that's used on all Tegra30-based boards we support,
we'll end up using 1.0125V instead.
At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates
that VDD_CORE must be at least 1.2V on all SKUs. According to
tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree),
that voltage is safe for all SKUs.
An alternative would be to port much of the code from tegra3_dvfs.c and
tegra3_speedo.c in the kernel tree mentioned above. That's more work
than I want to take on right now.
While all the currently supported boards use the same regulator chip for
VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we
add some small conditional code to select how VDD_CORE is programmed. If
this becomes more complex in the future as new boards are added, or we
end up adding code to detect the SoC SKU and dynamically determine the
allowed frequency and required voltages, we should probably make this a
runtime call into a function provided by the board file and/or relevant
PMIC driver.
Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Bard Liao <bardliao@realtek.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-09 00:33:45 +09:00
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#define TPS62366A_I2C_ADDR 0xC0
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#define TPS62366A_SET1_REG 0x01
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#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
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#define TPS62361B_I2C_ADDR 0xC0
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#define TPS62361B_SET3_REG 0x03
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#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
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2012-12-11 22:34:13 +09:00
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#define TPS65911_I2C_ADDR 0x5A
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#define TPS65911_VDDCTRL_OP_REG 0x28
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#define TPS65911_VDDCTRL_SR_REG 0x27
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ARM: tegra: use a CPU freq that all SKUs can support
U-Boot on Tegra30 currently selects a main CPU frequency that cannot be
supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values
on some others. This can result in unreliable operation of the main CPUs.
Resolve this by switching to a CPU frequency that can be supported by any
SKU. According to the following link, the maximum supported CPU frequency
of the slowest Tegra30 SKU is 600MHz:
repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary
branch l4t/l4t-r16-r2
path arch/arm/mach-tegra/tegra3_dvfs.c
table cpu_dvfs_table[]
According to that same table, the minimum VDD_CPU required to operate at
that frequency across all SKUs is 1.007V. Given the adjustment resolution
of the TPS65911 PMIC that's used on all Tegra30-based boards we support,
we'll end up using 1.0125V instead.
At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates
that VDD_CORE must be at least 1.2V on all SKUs. According to
tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree),
that voltage is safe for all SKUs.
An alternative would be to port much of the code from tegra3_dvfs.c and
tegra3_speedo.c in the kernel tree mentioned above. That's more work
than I want to take on right now.
While all the currently supported boards use the same regulator chip for
VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we
add some small conditional code to select how VDD_CORE is programmed. If
this becomes more complex in the future as new boards are added, or we
end up adding code to detect the SoC SKU and dynamically determine the
allowed frequency and required voltages, we should probably make this a
runtime call into a function provided by the board file and/or relevant
PMIC driver.
Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Bard Liao <bardliao@realtek.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-09 00:33:45 +09:00
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#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
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2012-12-11 22:34:13 +09:00
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#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
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#define I2C_SEND_2_BYTES 0x0A02
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static void enable_cpu_power_rail(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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debug("enable_cpu_power_rail entry\n");
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reg = readl(&pmc->pmc_cntrl);
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reg |= CPUPWRREQ_OE;
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writel(reg, &pmc->pmc_cntrl);
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ARM: tegra: use a CPU freq that all SKUs can support
U-Boot on Tegra30 currently selects a main CPU frequency that cannot be
supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values
on some others. This can result in unreliable operation of the main CPUs.
Resolve this by switching to a CPU frequency that can be supported by any
SKU. According to the following link, the maximum supported CPU frequency
of the slowest Tegra30 SKU is 600MHz:
repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary
branch l4t/l4t-r16-r2
path arch/arm/mach-tegra/tegra3_dvfs.c
table cpu_dvfs_table[]
According to that same table, the minimum VDD_CPU required to operate at
that frequency across all SKUs is 1.007V. Given the adjustment resolution
of the TPS65911 PMIC that's used on all Tegra30-based boards we support,
we'll end up using 1.0125V instead.
At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates
that VDD_CORE must be at least 1.2V on all SKUs. According to
tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree),
that voltage is safe for all SKUs.
An alternative would be to port much of the code from tegra3_dvfs.c and
tegra3_speedo.c in the kernel tree mentioned above. That's more work
than I want to take on right now.
While all the currently supported boards use the same regulator chip for
VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we
add some small conditional code to select how VDD_CORE is programmed. If
this becomes more complex in the future as new boards are added, or we
end up adding code to detect the SoC SKU and dynamically determine the
allowed frequency and required voltages, we should probably make this a
runtime call into a function provided by the board file and/or relevant
PMIC driver.
Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Bard Liao <bardliao@realtek.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-09 00:33:45 +09:00
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/* Set VDD_CORE to 1.200V. */
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#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
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tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
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#endif
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#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
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tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
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#endif
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udelay(1000);
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2012-12-11 22:34:13 +09:00
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/*
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* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
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ARM: tegra: use a CPU freq that all SKUs can support
U-Boot on Tegra30 currently selects a main CPU frequency that cannot be
supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values
on some others. This can result in unreliable operation of the main CPUs.
Resolve this by switching to a CPU frequency that can be supported by any
SKU. According to the following link, the maximum supported CPU frequency
of the slowest Tegra30 SKU is 600MHz:
repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary
branch l4t/l4t-r16-r2
path arch/arm/mach-tegra/tegra3_dvfs.c
table cpu_dvfs_table[]
According to that same table, the minimum VDD_CPU required to operate at
that frequency across all SKUs is 1.007V. Given the adjustment resolution
of the TPS65911 PMIC that's used on all Tegra30-based boards we support,
we'll end up using 1.0125V instead.
At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates
that VDD_CORE must be at least 1.2V on all SKUs. According to
tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree),
that voltage is safe for all SKUs.
An alternative would be to port much of the code from tegra3_dvfs.c and
tegra3_speedo.c in the kernel tree mentioned above. That's more work
than I want to take on right now.
While all the currently supported boards use the same regulator chip for
VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we
add some small conditional code to select how VDD_CORE is programmed. If
this becomes more complex in the future as new boards are added, or we
end up adding code to detect the SoC SKU and dynamically determine the
allowed frequency and required voltages, we should probably make this a
runtime call into a function provided by the board file and/or relevant
PMIC driver.
Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Bard Liao <bardliao@realtek.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-09 00:33:45 +09:00
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* First set VDD to 1.0125V, then enable the VDD regulator.
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2012-12-11 22:34:13 +09:00
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*/
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tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
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udelay(1000);
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tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
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udelay(10 * 1000);
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}
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/**
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* The T30 requires some special clock initialization, including setting up
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* the dvc i2c, turning on mselect and selecting the G CPU cluster
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*/
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void t30_init_clocks(void)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
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u32 val;
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debug("t30_init_clocks entry\n");
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/* Set active CPU cluster to G */
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clrbits_le32(flow->cluster_control, 1 << 0);
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writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
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val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
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(1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
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(0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
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(0 << CLK_SYS_RATE_APB_RATE_SHIFT);
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writel(val, &clkrst->crc_clk_sys_rate);
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/* Put i2c, mselect in reset and enable clocks */
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reset_set_enable(PERIPH_ID_DVC_I2C, 1);
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clock_set_enable(PERIPH_ID_DVC_I2C, 1);
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reset_set_enable(PERIPH_ID_MSELECT, 1);
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clock_set_enable(PERIPH_ID_MSELECT, 1);
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2013-04-04 06:39:30 +09:00
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/* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
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clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
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2012-12-11 22:34:13 +09:00
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/*
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* Our high-level clock routines are not available prior to
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* relocation. We use the low-level functions which require a
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* hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
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*/
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clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
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/*
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* Give clocks time to stabilize, then take i2c and mselect out of
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* reset
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*/
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udelay(1000);
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reset_set_enable(PERIPH_ID_DVC_I2C, 0);
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reset_set_enable(PERIPH_ID_MSELECT, 0);
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}
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static void set_cpu_running(int run)
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{
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
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debug("set_cpu_running entry, run = %d\n", run);
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writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
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}
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void start_cpu(u32 reset_vector)
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{
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debug("start_cpu entry, reset_vector = %x\n", reset_vector);
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t30_init_clocks();
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/* Enable VDD_CPU */
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enable_cpu_power_rail();
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set_cpu_running(0);
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/* Hold the CPUs in reset */
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reset_A9_cpu(1);
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/* Disable the CPU clock */
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enable_cpu_clock(0);
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/* Enable CoreSight */
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clock_enable_coresight(1);
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/*
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* Set the entry point for CPU execution from reset,
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* if it's a non-zero value.
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*/
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if (reset_vector)
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writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
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/* Enable the CPU clock */
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enable_cpu_clock(1);
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/* If the CPU doesn't already have power, power it up */
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powerup_cpu();
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/* Take the CPU out of reset */
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reset_A9_cpu(0);
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set_cpu_running(1);
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}
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