94 lines
1.5 KiB
C
94 lines
1.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/uclass.h>
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#include <errno.h>
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#include <asm/arch/sci/sci.h>
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#include <asm/arch-imx/cpu.h>
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#include <asm/armv8/cpu.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 get_cpu_rev(void)
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{
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u32 id = 0, rev = 0;
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int ret;
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ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
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if (ret)
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return 0;
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rev = (id >> 5) & 0xf;
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id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
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return (id << 12) | rev;
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}
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#ifdef CONFIG_DISPLAY_CPUINFO
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const char *get_imx8_type(u32 imxtype)
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{
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switch (imxtype) {
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case MXC_CPU_IMX8QXP:
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return "8QXP";
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default:
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return "??";
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}
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}
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const char *get_imx8_rev(u32 rev)
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{
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switch (rev) {
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case CHIP_REV_A:
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return "A";
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case CHIP_REV_B:
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return "B";
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default:
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return "?";
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}
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}
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const char *get_core_name(void)
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{
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if (is_cortex_a35())
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return "A35";
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else
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return "?";
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}
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int print_cpuinfo(void)
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{
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struct udevice *dev;
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struct clk cpu_clk;
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int ret;
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ret = uclass_get_device(UCLASS_CPU, 0, &dev);
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if (ret)
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return 0;
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ret = clk_get_by_index(dev, 0, &cpu_clk);
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if (ret) {
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dev_err(dev, "failed to clk\n");
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return 0;
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}
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u32 cpurev;
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cpurev = get_cpu_rev();
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printf("CPU: Freescale i.MX%s rev%s %s at %ld MHz\n",
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get_imx8_type((cpurev & 0xFF000) >> 12),
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get_imx8_rev((cpurev & 0xFFF)),
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get_core_name(),
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clk_get_rate(&cpu_clk) / 1000000);
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return 0;
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}
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#endif
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