2015-12-11 15:02:59 +09:00
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: Intel
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*/
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#ifndef __FSP_CONFIGS_H__
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#define __FSP_CONFIGS_H__
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2017-05-31 17:04:14 +09:00
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#ifndef __ASSEMBLY__
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2015-12-11 15:02:59 +09:00
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struct fsp_config_data {
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struct fsp_cfg_common common;
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struct upd_region fsp_upd;
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};
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2015-12-11 15:03:03 +09:00
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struct fspinit_rtbuf {
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struct common_buf common; /* FSP common runtime data structure */
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};
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2017-05-31 17:04:14 +09:00
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#endif
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/* FSP user configuration settings */
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#define MRC_INIT_TSEG_SIZE_1MB 1
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#define MRC_INIT_TSEG_SIZE_2MB 2
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#define MRC_INIT_TSEG_SIZE_4MB 4
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#define MRC_INIT_TSEG_SIZE_8MB 8
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#define MRC_INIT_MMIO_SIZE_1024MB 0x400
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#define MRC_INIT_MMIO_SIZE_1536MB 0x600
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#define MRC_INIT_MMIO_SIZE_2048MB 0x800
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#define EMMC_BOOT_MODE_DISABLED 0
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#define EMMC_BOOT_MODE_AUTO 1
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#define EMMC_BOOT_MODE_EMMC41 2
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#define EMMC_BOOT_MODE_EMCC45 3
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#define SATA_MODE_IDE 0
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#define SATA_MODE_AHCI 1
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#define IGD_DVMT50_PRE_ALLOC_32MB 0x01
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#define IGD_DVMT50_PRE_ALLOC_64MB 0x02
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#define IGD_DVMT50_PRE_ALLOC_96MB 0x03
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#define IGD_DVMT50_PRE_ALLOC_128MB 0x04
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#define IGD_DVMT50_PRE_ALLOC_160MB 0x05
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#define IGD_DVMT50_PRE_ALLOC_192MB 0x06
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#define IGD_DVMT50_PRE_ALLOC_224MB 0x07
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#define IGD_DVMT50_PRE_ALLOC_256MB 0x08
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#define IGD_DVMT50_PRE_ALLOC_288MB 0x09
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#define IGD_DVMT50_PRE_ALLOC_320MB 0x0a
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#define IGD_DVMT50_PRE_ALLOC_352MB 0x0b
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#define IGD_DVMT50_PRE_ALLOC_384MB 0x0c
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#define IGD_DVMT50_PRE_ALLOC_416MB 0x0d
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#define IGD_DVMT50_PRE_ALLOC_448MB 0x0e
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#define IGD_DVMT50_PRE_ALLOC_480MB 0x0f
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#define IGD_DVMT50_PRE_ALLOC_512MB 0x10
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#define APERTURE_SIZE_128MB 1
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#define APERTURE_SIZE_256MB 2
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#define APERTURE_SIZE_512MB 3
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#define GTT_SIZE_1MB 1
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#define GTT_SIZE_2MB 2
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#define OS_SELECTION_ANDROID 1
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#define OS_SELECTION_LINUX 4
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#define DRAM_SPEED_800MTS 0
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#define DRAM_SPEED_1066MTS 1
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#define DRAM_SPEED_1333MTS 2
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#define DRAM_SPEED_1600MTS 3
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#define DRAM_TYPE_DDR3 0
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#define DRAM_TYPE_DDR3L 1
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#define DRAM_TYPE_DDR3ECC 2
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#define DRAM_TYPE_LPDDR2 4
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#define DRAM_TYPE_LPDDR3 5
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#define DRAM_TYPE_DDR4 6
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#define DIMM_WIDTH_X8 0
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#define DIMM_WIDTH_X16 1
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#define DIMM_WIDTH_X32 2
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#define DIMM_DENSITY_1GBIT 0
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#define DIMM_DENSITY_2GBIT 1
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#define DIMM_DENSITY_4GBIT 2
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#define DIMM_DENSITY_8GBIT 3
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#define DIMM_BUS_WIDTH_8BITS 0
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#define DIMM_BUS_WIDTH_16BITS 1
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#define DIMM_BUS_WIDTH_32BITS 2
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#define DIMM_BUS_WIDTH_64BITS 3
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#define DIMM_SIDES_1RANKS 0
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#define DIMM_SIDES_2RANKS 1
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2015-12-11 15:03:03 +09:00
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2015-12-11 15:02:59 +09:00
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#endif /* __FSP_CONFIGS_H__ */
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