2018-05-07 06:58:06 +09:00
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// SPDX-License-Identifier: GPL-2.0+
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2016-07-20 18:55:12 +09:00
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/*
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* Copyright (C) 2016 Atmel Corporation
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* Wenyou.Yang <wenyou.yang@atmel.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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2017-05-18 08:18:03 +09:00
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#include <dm.h>
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2020-05-11 02:40:05 +09:00
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#include <log.h>
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2016-07-20 18:55:12 +09:00
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#include <dm/lists.h>
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2017-02-19 03:46:21 +09:00
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#include <dm/util.h>
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2016-07-20 18:55:12 +09:00
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#include "pmc.h"
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DECLARE_GLOBAL_DATA_PTR;
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static const struct udevice_id at91_pmc_match[] = {
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2017-04-14 15:53:24 +09:00
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{ .compatible = "atmel,at91rm9200-pmc" },
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{ .compatible = "atmel,at91sam9260-pmc" },
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{ .compatible = "atmel,at91sam9g45-pmc" },
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{ .compatible = "atmel,at91sam9n12-pmc" },
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{ .compatible = "atmel,at91sam9x5-pmc" },
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{ .compatible = "atmel,sama5d3-pmc" },
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2016-07-20 18:55:12 +09:00
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{ .compatible = "atmel,sama5d2-pmc" },
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{}
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};
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2020-06-25 13:10:04 +09:00
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U_BOOT_DRIVER(atmel_at91rm9200_pmc) = {
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.name = "atmel_at91rm9200_pmc",
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2016-09-13 11:25:55 +09:00
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.id = UCLASS_SIMPLE_BUS,
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.of_match = at91_pmc_match,
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};
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2020-06-25 13:10:06 +09:00
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U_BOOT_DRIVER_ALIAS(atmel_at91rm9200_pmc, atmel_at91sam9260_pmc)
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2016-09-27 12:00:29 +09:00
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/*---------------------------------------------------------*/
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2016-07-20 18:55:12 +09:00
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int at91_pmc_core_probe(struct udevice *dev)
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{
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struct pmc_platdata *plat = dev_get_platdata(dev);
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dev = dev_get_parent(dev);
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2017-05-18 08:18:05 +09:00
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plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev);
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2016-07-20 18:55:12 +09:00
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return 0;
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}
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2016-09-27 12:00:29 +09:00
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/**
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* at91_clk_sub_device_bind() - for the at91 clock driver
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* Recursively bind its children as clk devices.
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*
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* @return: 0 on success, or negative error code on failure
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*/
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int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
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{
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const void *fdt = gd->fdt_blob;
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int offset = dev_of_offset(dev);
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bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
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const char *name;
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int ret;
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for (offset = fdt_first_subnode(fdt, offset);
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offset > 0;
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offset = fdt_next_subnode(fdt, offset)) {
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if (pre_reloc_only &&
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2020-04-03 18:39:18 +09:00
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!ofnode_pre_reloc(offset_to_ofnode(offset)))
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continue;
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/*
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* If this node has "compatible" property, this is not
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* a clock sub-node, but a normal device. skip.
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*/
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fdt_get_property(fdt, offset, "compatible", &ret);
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if (ret >= 0)
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continue;
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if (ret != -FDT_ERR_NOTFOUND)
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return ret;
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2016-07-20 18:55:12 +09:00
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name = fdt_get_name(fdt, offset, NULL);
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if (!name)
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return -EINVAL;
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ret = device_bind_driver_to_node(dev, drv_name, name,
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offset_to_ofnode(offset), NULL);
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2016-07-20 18:55:12 +09:00
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if (ret)
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return ret;
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}
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return 0;
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}
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2017-05-19 11:09:40 +09:00
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int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
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2016-09-27 12:00:29 +09:00
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{
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int periph;
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if (args->args_count) {
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debug("Invalid args_count: %d\n", args->args_count);
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return -EINVAL;
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}
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2017-01-18 08:52:55 +09:00
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periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
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-1);
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2016-09-27 12:00:29 +09:00
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if (periph < 0)
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return -EINVAL;
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clk->id = periph;
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return 0;
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}
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int at91_clk_probe(struct udevice *dev)
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{
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struct udevice *dev_periph_container, *dev_pmc;
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struct pmc_platdata *plat = dev_get_platdata(dev);
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dev_periph_container = dev_get_parent(dev);
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dev_pmc = dev_get_parent(dev_periph_container);
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2017-05-18 08:18:05 +09:00
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plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev_pmc);
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2016-09-27 12:00:29 +09:00
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return 0;
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}
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