u-boot-brain/drivers/clk/sifive/Kconfig

# SPDX-License-Identifier: GPL-2.0

config CLK_ANALOGBITS_WRPLL_CLN28HPC
	bool

config CLK_SIFIVE
	bool "SiFive SoC driver support"
	depends on CLK
	help
	  SoC drivers for SiFive Linux-capable SoCs.

config CLK_SIFIVE_FU540_PRCI
	bool "PRCI driver for SiFive FU540 SoCs"
	depends on CLK_SIFIVE
	select CLK_ANALOGBITS_WRPLL_CLN28HPC
	help
	  Supports the Power Reset Clock interface (PRCI) IP block found in
	  FU540 SoCs.  If this kernel is meant to run on a SiFive FU540 SoC,
	  enable this driver.
clk: Add SiFive FU540 PRCI clock driver Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> 2019-02-25 17:14:49 +09:00			`# SPDX-License-Identifier: GPL-2.0`

			`config CLK_ANALOGBITS_WRPLL_CLN28HPC`
			`bool`

			`config CLK_SIFIVE`
			`bool "SiFive SoC driver support"`
			`depends on CLK`
			`help`
			`SoC drivers for SiFive Linux-capable SoCs.`

			`config CLK_SIFIVE_FU540_PRCI`
			`bool "PRCI driver for SiFive FU540 SoCs"`
			`depends on CLK_SIFIVE`
			`select CLK_ANALOGBITS_WRPLL_CLN28HPC`
			`help`
			`Supports the Power Reset Clock interface (PRCI) IP block found in`
			`FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,`
			`enable this driver.`