u-boot-brain/include/fsl_wdog.h

/*
 * (C) Copyright 2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

struct watchdog_regs {
	u16	wcr;	/* Control */
	u16	wsr;	/* Service */
	u16	wrsr;	/* Reset Status */
};

#define WCR_WDZST	0x01
#define WCR_WDBG	0x02
#define WCR_WDE		0x04
#define WCR_WDT		0x08
#define WCR_SRS		0x10
#define SET_WCR_WT(x)	(x << 8)
#define WCR_WT_MSK	SET_WCR_WT(0xFF)
imx_watchdog: Add a header file for watchdog registers Create fsl_wdog.h to store the watchdog registers and bit fields. This can be useful when accesses to the watchdog block are made from other parts, such as arch/arm/ cpu code. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> 2015-10-04 02:20:59 +09:00			`/*`
			`* (C) Copyright 2015 Freescale Semiconductor, Inc.`
			`*`
			`* SPDX-License-Identifier: GPL-2.0+`
			`*/`

			`struct watchdog_regs {`
			`u16 wcr; /* Control */`
			`u16 wsr; /* Service */`
			`u16 wrsr; /* Reset Status */`
			`};`

			`#define WCR_WDZST 0x01`
			`#define WCR_WDBG 0x02`
			`#define WCR_WDE 0x04`
			`#define WCR_WDT 0x08`
			`#define WCR_SRS 0x10`
			`#define SET_WCR_WT(x) (x << 8)`
imx_watchdog: always set minimal timeout in reset_cpu The problem is that timeout bits in WCR register were leaved unchanged. So previously set timeout value was applied and therefore 'reset' command takes any value up to two minutes, depending on previous watchdog settings, instead of minimal 0.5 seconds. Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> 2015-12-21 03:09:58 +09:00			`#define WCR_WT_MSK SET_WCR_WT(0xFF)`