2019-02-19 21:42:01 +09:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Amlogic G12A DWC3 Glue layer
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*
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <common.h>
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2020-05-11 02:40:05 +09:00
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#include <log.h>
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2019-02-19 21:42:01 +09:00
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#include <asm-generic/io.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dwc3-uboot.h>
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#include <generic-phy.h>
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2020-05-11 02:40:11 +09:00
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#include <linux/delay.h>
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2019-02-19 21:42:01 +09:00
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <malloc.h>
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#include <regmap.h>
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#include <usb.h>
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#include "core.h"
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#include "gadget.h"
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#include <reset.h>
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#include <clk.h>
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#include <power/regulator.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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/* USB2 Ports Control Registers */
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#define U2P_REG_SIZE 0x20
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#define U2P_R0 0x0
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#define U2P_R0_HOST_DEVICE BIT(0)
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#define U2P_R0_POWER_OK BIT(1)
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#define U2P_R0_HAST_MODE BIT(2)
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#define U2P_R0_POWER_ON_RESET BIT(3)
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#define U2P_R0_ID_PULLUP BIT(4)
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#define U2P_R0_DRV_VBUS BIT(5)
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#define U2P_R1 0x4
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#define U2P_R1_PHY_READY BIT(0)
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#define U2P_R1_ID_DIG BIT(1)
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#define U2P_R1_OTG_SESSION_VALID BIT(2)
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#define U2P_R1_VBUS_VALID BIT(3)
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/* USB Glue Control Registers */
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#define USB_R0 0x80
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#define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
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#define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
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#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
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#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
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#define USB_R0_U2D_ACT BIT(31)
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#define USB_R1 0x84
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#define USB_R1_U3H_BIGENDIAN_GS BIT(0)
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#define USB_R1_U3H_PME_ENABLE BIT(1)
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#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2)
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#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(9, 7)
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#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(13, 12)
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#define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
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#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
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#define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
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#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
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#define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
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#define USB_R2 0x88
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#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
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#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
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#define USB_R3 0x8c
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#define USB_R3_P30_SSC_ENABLE BIT(0)
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#define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
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#define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
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#define USB_R3_P30_REF_SSP_EN BIT(13)
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#define USB_R4 0x90
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#define USB_R4_P21_PORT_RESET_0 BIT(0)
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#define USB_R4_P21_SLEEP_M0 BIT(1)
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#define USB_R4_MEM_PD_MASK GENMASK(3, 2)
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#define USB_R4_P21_ONLY BIT(4)
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#define USB_R5 0x94
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#define USB_R5_ID_DIG_SYNC BIT(0)
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#define USB_R5_ID_DIG_REG BIT(1)
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#define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
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#define USB_R5_ID_DIG_EN_0 BIT(4)
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#define USB_R5_ID_DIG_EN_1 BIT(5)
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#define USB_R5_ID_DIG_CURR BIT(6)
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#define USB_R5_ID_DIG_IRQ BIT(7)
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#define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
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#define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
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enum {
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USB2_HOST_PHY = 0,
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USB2_OTG_PHY,
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USB3_HOST_PHY,
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PHY_COUNT,
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};
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static const char *phy_names[PHY_COUNT] = {
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"usb2-phy0", "usb2-phy1", "usb3-phy0",
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};
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struct dwc3_meson_g12a {
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struct udevice *dev;
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struct regmap *regmap;
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struct clk clk;
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struct reset_ctl reset;
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struct phy phys[PHY_COUNT];
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enum usb_dr_mode otg_mode;
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enum usb_dr_mode otg_phy_mode;
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unsigned int usb2_ports;
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unsigned int usb3_ports;
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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struct udevice *vbus_supply;
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#endif
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};
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#define U2P_REG_SIZE 0x20
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#define USB_REG_OFFSET 0x80
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static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
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int i, enum usb_dr_mode mode)
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{
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switch (mode) {
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case USB_DR_MODE_HOST:
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case USB_DR_MODE_OTG:
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case USB_DR_MODE_UNKNOWN:
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regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
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U2P_R0_HOST_DEVICE,
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U2P_R0_HOST_DEVICE);
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break;
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case USB_DR_MODE_PERIPHERAL:
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regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
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U2P_R0_HOST_DEVICE, 0);
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break;
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}
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}
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static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
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{
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int i;
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if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
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priv->otg_phy_mode = USB_DR_MODE_PERIPHERAL;
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else
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priv->otg_phy_mode = USB_DR_MODE_HOST;
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for (i = 0 ; i < USB3_HOST_PHY ; ++i) {
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if (!priv->phys[i].dev)
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continue;
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regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
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U2P_R0_POWER_ON_RESET,
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U2P_R0_POWER_ON_RESET);
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if (i == USB2_OTG_PHY) {
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regmap_update_bits(priv->regmap,
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U2P_R0 + (U2P_REG_SIZE * i),
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U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
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U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS);
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dwc3_meson_g12a_usb2_set_mode(priv, i,
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priv->otg_phy_mode);
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} else
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dwc3_meson_g12a_usb2_set_mode(priv, i,
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USB_DR_MODE_HOST);
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regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
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U2P_R0_POWER_ON_RESET, 0);
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}
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return 0;
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}
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static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
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{
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regmap_update_bits(priv->regmap, USB_R3,
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USB_R3_P30_SSC_RANGE_MASK |
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USB_R3_P30_REF_SSP_EN,
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USB_R3_P30_SSC_ENABLE |
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FIELD_PREP(USB_R3_P30_SSC_RANGE_MASK, 2) |
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USB_R3_P30_REF_SSP_EN);
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udelay(2);
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regmap_update_bits(priv->regmap, USB_R2,
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USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK,
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FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15));
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regmap_update_bits(priv->regmap, USB_R2,
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USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK,
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FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20));
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udelay(2);
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regmap_update_bits(priv->regmap, USB_R1,
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USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT,
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USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT);
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regmap_update_bits(priv->regmap, USB_R1,
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USB_R1_P30_PCS_TX_SWING_FULL_MASK,
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FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
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}
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static void dwc3_meson_g12a_usb_init_mode(struct dwc3_meson_g12a *priv)
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{
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if (priv->otg_phy_mode == USB_DR_MODE_PERIPHERAL) {
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regmap_update_bits(priv->regmap, USB_R0,
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USB_R0_U2D_ACT, USB_R0_U2D_ACT);
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regmap_update_bits(priv->regmap, USB_R0,
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USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
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regmap_update_bits(priv->regmap, USB_R4,
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USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
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} else {
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regmap_update_bits(priv->regmap, USB_R0,
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USB_R0_U2D_ACT, 0);
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regmap_update_bits(priv->regmap, USB_R4,
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USB_R4_P21_SLEEP_M0, 0);
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}
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}
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static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
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{
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int ret;
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ret = dwc3_meson_g12a_usb2_init(priv);
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if (ret)
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return ret;
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regmap_update_bits(priv->regmap, USB_R1,
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USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
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FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
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regmap_update_bits(priv->regmap, USB_R5,
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USB_R5_ID_DIG_EN_0,
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USB_R5_ID_DIG_EN_0);
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regmap_update_bits(priv->regmap, USB_R5,
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USB_R5_ID_DIG_EN_1,
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USB_R5_ID_DIG_EN_1);
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regmap_update_bits(priv->regmap, USB_R5,
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USB_R5_ID_DIG_TH_MASK,
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FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
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/* If we have an actual SuperSpeed port, initialize it */
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if (priv->usb3_ports)
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dwc3_meson_g12a_usb3_init(priv);
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dwc3_meson_g12a_usb_init_mode(priv);
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return 0;
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}
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int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode)
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{
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struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
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if (!priv)
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return -EINVAL;
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if (mode != USB_DR_MODE_HOST && mode != USB_DR_MODE_PERIPHERAL)
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return -EINVAL;
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if (!priv->phys[USB2_OTG_PHY].dev)
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return -EINVAL;
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if (mode == priv->otg_mode)
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return 0;
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if (mode == USB_DR_MODE_HOST)
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debug("%s: switching to Host Mode\n", __func__);
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else
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debug("%s: switching to Device Mode\n", __func__);
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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if (priv->vbus_supply) {
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int ret = regulator_set_enable(priv->vbus_supply,
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(mode == USB_DR_MODE_PERIPHERAL));
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if (ret)
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return ret;
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}
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#endif
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priv->otg_phy_mode = mode;
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dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode);
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dwc3_meson_g12a_usb_init_mode(priv);
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return 0;
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}
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static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
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{
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int i, ret;
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for (i = 0 ; i < PHY_COUNT ; ++i) {
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ret = generic_phy_get_by_name(priv->dev, phy_names[i],
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&priv->phys[i]);
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if (ret == -ENOENT)
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continue;
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if (ret)
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return ret;
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if (i == USB3_HOST_PHY)
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priv->usb3_ports++;
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else
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priv->usb2_ports++;
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}
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debug("%s: usb2 ports: %d\n", __func__, priv->usb2_ports);
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debug("%s: usb3 ports: %d\n", __func__, priv->usb3_ports);
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return 0;
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}
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static int dwc3_meson_g12a_reset_init(struct dwc3_meson_g12a *priv)
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{
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int ret;
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ret = reset_get_by_index(priv->dev, 0, &priv->reset);
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if (ret)
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return ret;
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|
|
|
ret = reset_assert(&priv->reset);
|
|
|
|
udelay(1);
|
|
|
|
ret |= reset_deassert(&priv->reset);
|
|
|
|
if (ret) {
|
|
|
|
reset_free(&priv->reset);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_meson_g12a_clk_init(struct dwc3_meson_g12a *priv)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = clk_get_by_index(priv->dev, 0, &priv->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
|
|
ret = clk_enable(&priv->clk);
|
|
|
|
if (ret) {
|
|
|
|
clk_free(&priv->clk);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_meson_g12a_probe(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
|
|
|
|
int ret, i;
|
|
|
|
|
|
|
|
priv->dev = dev;
|
|
|
|
|
|
|
|
ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = dwc3_meson_g12a_clk_init(priv);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = dwc3_meson_g12a_reset_init(priv);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = dwc3_meson_g12a_get_phys(priv);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
|
|
|
ret = device_get_supply_regulator(dev, "vbus-supply",
|
|
|
|
&priv->vbus_supply);
|
|
|
|
if (ret && ret != -ENOENT) {
|
|
|
|
pr_err("Failed to get PHY regulator\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (priv->vbus_supply) {
|
|
|
|
ret = regulator_set_enable(priv->vbus_supply, true);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2020-03-04 09:59:50 +09:00
|
|
|
priv->otg_mode = usb_get_dr_mode(dev->node);
|
2019-02-19 21:42:01 +09:00
|
|
|
|
|
|
|
ret = dwc3_meson_g12a_usb_init(priv);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
for (i = 0 ; i < PHY_COUNT ; ++i) {
|
|
|
|
if (!priv->phys[i].dev)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
ret = generic_phy_init(&priv->phys[i]);
|
|
|
|
if (ret)
|
|
|
|
goto err_phy_init;
|
|
|
|
}
|
|
|
|
|
2020-04-21 17:17:42 +09:00
|
|
|
for (i = 0; i < PHY_COUNT; ++i) {
|
|
|
|
if (!priv->phys[i].dev)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
ret = generic_phy_power_on(&priv->phys[i]);
|
|
|
|
if (ret)
|
|
|
|
goto err_phy_init;
|
|
|
|
}
|
|
|
|
|
2019-02-19 21:42:01 +09:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_phy_init:
|
|
|
|
for (i = 0 ; i < PHY_COUNT ; ++i) {
|
|
|
|
if (!priv->phys[i].dev)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
generic_phy_exit(&priv->phys[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_meson_g12a_remove(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
reset_release_all(&priv->reset, 1);
|
|
|
|
|
|
|
|
clk_release_all(&priv->clk, 1);
|
|
|
|
|
2020-04-21 17:17:42 +09:00
|
|
|
for (i = 0; i < PHY_COUNT; ++i) {
|
|
|
|
if (!priv->phys[i].dev)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
generic_phy_power_off(&priv->phys[i]);
|
|
|
|
}
|
|
|
|
|
2019-02-19 21:42:01 +09:00
|
|
|
for (i = 0 ; i < PHY_COUNT ; ++i) {
|
|
|
|
if (!priv->phys[i].dev)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
generic_phy_exit(&priv->phys[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
return dm_scan_fdt_dev(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct udevice_id dwc3_meson_g12a_ids[] = {
|
|
|
|
{ .compatible = "amlogic,meson-g12a-usb-ctrl" },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(dwc3_generic_wrapper) = {
|
|
|
|
.name = "dwc3-meson-g12a",
|
|
|
|
.id = UCLASS_SIMPLE_BUS,
|
|
|
|
.of_match = dwc3_meson_g12a_ids,
|
|
|
|
.probe = dwc3_meson_g12a_probe,
|
|
|
|
.remove = dwc3_meson_g12a_remove,
|
2020-12-04 08:55:18 +09:00
|
|
|
.plat_auto = sizeof(struct dwc3_meson_g12a),
|
2019-02-19 21:42:01 +09:00
|
|
|
|
|
|
|
};
|