2019-06-24 22:50:45 +09:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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#ifndef __MACH_IMX_CLK_H
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#define __MACH_IMX_CLK_H
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#include <linux/clk-provider.h>
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enum imx_pllv3_type {
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IMX_PLLV3_GENERIC,
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IMX_PLLV3_SYS,
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IMX_PLLV3_USB,
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IMX_PLLV3_USB_VF610,
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IMX_PLLV3_AV,
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IMX_PLLV3_ENET,
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IMX_PLLV3_ENET_IMX7,
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IMX_PLLV3_SYS_VF610,
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IMX_PLLV3_DDR_IMX7,
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};
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struct clk *clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, u8 cgr_val,
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u8 clk_gate_flags);
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base,
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u32 div_mask);
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static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0x3, 0);
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}
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2019-07-31 16:01:42 +09:00
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static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate2(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0x3, 0);
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}
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static inline struct clk *imx_clk_gate4_flags(const char *name,
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const char *parent, void __iomem *reg, u8 shift,
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unsigned long flags)
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{
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return clk_register_gate2(NULL, name, parent,
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flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0x3, 0);
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}
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2019-06-24 22:50:45 +09:00
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static inline struct clk *imx_clk_fixed_factor(const char *name,
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const char *parent, unsigned int mult, unsigned int div)
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{
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return clk_register_fixed_factor(NULL, name, parent,
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CLK_SET_RATE_PARENT, mult, div);
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}
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static inline struct clk *imx_clk_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
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reg, shift, width, 0);
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}
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2019-07-31 16:01:42 +09:00
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static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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return clk_register_divider(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, width, 0);
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}
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2019-06-24 22:50:45 +09:00
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struct clk *imx_clk_pfd(const char *name, const char *parent_name,
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void __iomem *reg, u8 idx);
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struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char * const *parents,
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int num_parents, void (*fixup)(u32 *val));
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2019-07-31 16:01:42 +09:00
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static inline struct clk *imx_clk_mux_flags(const char *name,
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void __iomem *reg, u8 shift, u8 width,
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const char * const *parents, int num_parents,
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unsigned long flags)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
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width, 0);
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}
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2019-06-24 22:50:45 +09:00
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static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char * const *parents,
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int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT, reg, shift,
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width, 0);
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}
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2019-07-31 16:01:42 +09:00
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static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char * const *parents,
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int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, width, 0);
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}
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static inline struct clk *imx_clk_gate(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0, NULL);
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}
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static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
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void __iomem *reg, u8 shift, unsigned long flags)
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{
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return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
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shift, 0, NULL);
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}
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static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0, NULL);
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}
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struct clk *imx8m_clk_composite_flags(const char *name,
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const char * const *parent_names,
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int num_parents, void __iomem *reg, unsigned long flags);
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#define __imx8m_clk_composite(name, parent_names, reg, flags) \
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imx8m_clk_composite_flags(name, parent_names, \
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ARRAY_SIZE(parent_names), reg, \
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flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
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#define imx8m_clk_composite(name, parent_names, reg) \
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__imx8m_clk_composite(name, parent_names, reg, 0)
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#define imx8m_clk_composite_critical(name, parent_names, reg) \
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__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
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2019-06-24 22:50:45 +09:00
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#endif /* __MACH_IMX_CLK_H */
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