mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 17:08:52 +09:00
251 lines
7.6 KiB
C
251 lines
7.6 KiB
C
![]() |
/* SPDX-License-Identifier: GPL-2.0
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* Copyright 2016-2018 NXP Semiconductors
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* Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_DEEP_SLEEP
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
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#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
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/* XHCI Support - enabled by default */
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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#define DDR_SDRAM_CFG 0x470c0008
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#define DDR_CS0_BNDS 0x008000bf
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#define DDR_CS0_CONFIG 0x80014302
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#define DDR_TIMING_CFG_0 0x50550004
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#define DDR_TIMING_CFG_1 0xbcb38c56
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#define DDR_TIMING_CFG_2 0x0040d120
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#define DDR_TIMING_CFG_3 0x010e1000
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#define DDR_TIMING_CFG_4 0x00000001
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#define DDR_TIMING_CFG_5 0x03401400
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#define DDR_SDRAM_CFG_2 0x00401010
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#define DDR_SDRAM_MODE 0x00061c60
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#define DDR_SDRAM_MODE_2 0x00180000
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#define DDR_SDRAM_INTERVAL 0x18600618
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#define DDR_DDR_WRLVL_CNTL 0x8655f605
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#define DDR_DDR_WRLVL_CNTL_2 0x05060607
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#define DDR_DDR_WRLVL_CNTL_3 0x05050505
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#define DDR_DDR_CDR1 0x80040000
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#define DDR_DDR_CDR2 0x00000001
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#define DDR_SDRAM_CLK_CNTL 0x02000000
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#define DDR_DDR_ZQ_CNTL 0x89080600
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#define DDR_CS0_CONFIG_2 0
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#define DDR_SDRAM_CFG_MEM_EN 0x80000000
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#define SDRAM_CFG2_D_INIT 0x00000010
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#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
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#define SDRAM_CFG2_FRC_SR 0x80000000
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#define SDRAM_CFG_BI 0x00000001
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_SYS_FSL_PBL_PBI \
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"board/freescale/ls1021atsn/ls102xa_pbi.cfg"
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#endif
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SYS_FSL_PBL_RCW \
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"board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
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#ifdef CONFIG_SECURE_BOOT
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#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
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#endif /* ifdef CONFIG_SECURE_BOOT */
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#define CONFIG_SPL_MAX_SIZE 0x1a000
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#define CONFIG_SPL_STACK 0x1001d000
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#define CONFIG_SPL_PAD_TO 0x1c000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#ifdef CONFIG_U_BOOT_HDR_SIZE
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/*
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* HDR would be appended at end of image and copied to DDR along
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* with U-Boot image. Here u-boot max. size is 512K. So if binary
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* size increases then increase this size in case of secure boot as
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* it uses raw U-Boot image instead of FIT image.
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*/
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#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
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#else
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#define CONFIG_SYS_MONITOR_LEN 0x100000
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#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
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#endif
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x80000000
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#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#ifndef CONFIG_DM_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#endif
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#define CONFIG_BAUDRATE 115200
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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/* QSPI */
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#define FSL_QSPI_FLASH_SIZE (1 << 24)
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#define FSL_QSPI_FLASH_NUM 2
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/* PCIe */
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define COUNTER_FREQUENCY 12500000
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 256
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#define CONFIG_FSL_DEVICE_DISABLE
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(USB, usb, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
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"initrd_high=0xffffffff\0" \
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"fdt_high=0xffffffff\0" \
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"fdt_addr=0x64f00000\0" \
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"kernel_addr=0x61000000\0" \
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"kernelheader_addr=0x60800000\0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"kernel_addr_r=0x80008000\0" \
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"kernelheader_size=0x40000\0" \
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"fdt_addr_r=0x8f000000\0" \
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"ramdisk_addr_r=0xa0000000\0" \
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"load_addr=0x80008000\0" \
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"kernel_size=0x2800000\0" \
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"kernel_addr_sd=0x8000\0" \
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"kernel_size_sd=0x14000\0" \
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"kernelhdr_addr_sd=0x4000\0" \
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"kernelhdr_size_sd=0x10\0" \
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BOOTENV \
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"boot_scripts=ls1021atsn_boot.scr\0" \
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"boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
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"fi; " \
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"done\0" \
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"scan_dev_for_boot=" \
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"echo Scanning ${devtype} " \
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"${devnum}:${distro_bootpart}...; " \
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"for prefix in ${boot_prefixes}; do " \
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"run scan_dev_for_scripts; " \
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"run scan_dev_for_extlinux; " \
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"done;" \
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"\0" \
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"boot_a_script=" \
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"load ${devtype} ${devnum}:${distro_bootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"env exists secureboot && load ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"${scripthdraddr} ${prefix}${boot_script_hdr} " \
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"&& esbc_validate ${scripthdraddr};" \
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"source ${scriptaddr}\0" \
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"qspi_bootcmd=echo Trying load from qspi..;" \
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"sf probe && sf read $load_addr " \
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"$kernel_addr $kernel_size; env exists secureboot " \
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"&& sf read $kernelheader_addr_r $kernelheader_addr " \
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"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
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"bootm $load_addr#$board\0" \
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"sd_bootcmd=echo Trying load from SD ..;" \
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"mmcinfo && mmc read $load_addr " \
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"$kernel_addr_sd $kernel_size_sd && " \
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"env exists secureboot && mmc read $kernelheader_addr_r " \
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"$kernelhdr_addr_sd $kernelhdr_size_sd " \
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" && esbc_validate ${kernelheader_addr_r};" \
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"bootm $load_addr#$board\0"
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_LOAD_ADDR 0x82000000
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#define CONFIG_LS102XA_STREAM_ID
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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/* Environment */
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_SD_BOOT)
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#define CONFIG_ENV_OFFSET 0x300000
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x20000
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#elif defined(CONFIG_QSPI_BOOT)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET 0x300000
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#define CONFIG_ENV_SECT_SIZE 0x40000
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#endif
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#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */
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#endif
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