u-boot-brain/arch/arm/mach-rockchip/rk3288/Makefile

#
# Copyright (c) 2015 Google, Inc
#
# SPDX-License-Identifier:      GPL-2.0+
#

obj-y += clk_rk3288.o
obj-y += rk3288.o
obj-y += sdram_rk3288.o
obj-y += syscon_rk3288.o
rockchip: rk3288: Add SoC reset driver We can reset the SoC using some CRU (clock/reset unit) registers. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org> 2015-08-31 07:55:33 +09:00			`#`
			`# Copyright (c) 2015 Google, Inc`
			`#`
			`# SPDX-License-Identifier: GPL-2.0+`
			`#`

rockchip: Add a way to obtain the main clock device On Rockchip SoCs we typically have a main clock device that uses the Soc clock driver. There is also a fixed clock for the oscillator. Add a function to obtain the core clock. Signed-off-by: Simon Glass <sjg@chromium.org> 2016-07-18 06:23:16 +09:00			`obj-y += clk_rk3288.o`
rk3288: add arch_cpu_init for rk3288 We do some SoC level one time setting initialization in arch_cpu_init. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> 2016-08-12 18:58:12 +09:00			`obj-y += rk3288.o`
rockchip: rk3288: Add SDRAM init Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses device tree for configuration so should be able to support other RAM configurations. It may be possible to generalise the code to support other SoCs at some point. Signed-off-by: Simon Glass <sjg@chromium.org> 2015-08-31 07:55:36 +09:00			`obj-y += sdram_rk3288.o`
rockchip: rk3288: Add a simple syscon driver Add a driver that provides access to system controllers. Signed-off-by: Simon Glass <sjg@chromium.org> 2015-08-31 07:55:34 +09:00			`obj-y += syscon_rk3288.o`