u-boot-brain/arch/riscv/cpu/Makefile

# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>

extra-y = start.o

obj-y += cpu.o mtrap.o
riscv: Add a helper routine to print CPU information This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> 2018-09-26 22:55:14 +09:00			`# SPDX-License-Identifier: GPL-2.0+`
			`#`
			`# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>`

riscv: Make start.S available for all targets Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> 2018-09-26 22:55:17 +09:00			`extra-y = start.o`

riscv: Move trap handler codes to mtrap.S Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 23:12:41 +09:00			`obj-y += cpu.o mtrap.o`