2018-05-07 06:58:06 +09:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2011-11-28 15:37:32 +09:00
|
|
|
/*
|
|
|
|
* (C) Copyright 2011
|
|
|
|
* Ilya Yanok, EmCraft Systems
|
|
|
|
*/
|
2019-11-15 04:57:37 +09:00
|
|
|
#include <cpu_func.h>
|
2020-05-11 02:39:56 +09:00
|
|
|
#include <asm/cache.h>
|
2011-11-28 15:37:32 +09:00
|
|
|
#include <linux/types.h>
|
|
|
|
#include <common.h>
|
|
|
|
|
2019-05-03 22:41:00 +09:00
|
|
|
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
|
2012-03-16 03:33:17 +09:00
|
|
|
void invalidate_dcache_all(void)
|
2011-11-28 15:37:32 +09:00
|
|
|
{
|
2012-04-06 12:25:07 +09:00
|
|
|
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
|
2011-11-28 15:37:32 +09:00
|
|
|
}
|
|
|
|
|
2012-03-16 03:33:17 +09:00
|
|
|
void flush_dcache_all(void)
|
2011-11-28 15:37:32 +09:00
|
|
|
{
|
2012-03-16 03:33:17 +09:00
|
|
|
asm volatile(
|
|
|
|
"0:"
|
|
|
|
"mrc p15, 0, r15, c7, c14, 3\n"
|
|
|
|
"bne 0b\n"
|
|
|
|
"mcr p15, 0, %0, c7, c10, 4\n"
|
2012-04-06 12:25:07 +09:00
|
|
|
: : "r"(0) : "memory"
|
2012-03-16 03:33:17 +09:00
|
|
|
);
|
|
|
|
}
|
|
|
|
|
2011-11-28 15:37:32 +09:00
|
|
|
void invalidate_dcache_range(unsigned long start, unsigned long stop)
|
|
|
|
{
|
2012-03-16 03:33:17 +09:00
|
|
|
if (!check_cache_range(start, stop))
|
|
|
|
return;
|
|
|
|
|
|
|
|
while (start < stop) {
|
2012-04-06 12:25:07 +09:00
|
|
|
asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
|
2012-03-16 03:33:17 +09:00
|
|
|
start += CONFIG_SYS_CACHELINE_SIZE;
|
|
|
|
}
|
2011-11-28 15:37:32 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
void flush_dcache_range(unsigned long start, unsigned long stop)
|
|
|
|
{
|
2012-03-16 03:33:17 +09:00
|
|
|
if (!check_cache_range(start, stop))
|
|
|
|
return;
|
|
|
|
|
|
|
|
while (start < stop) {
|
2012-04-06 12:25:07 +09:00
|
|
|
asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
|
2012-03-16 03:33:17 +09:00
|
|
|
start += CONFIG_SYS_CACHELINE_SIZE;
|
|
|
|
}
|
|
|
|
|
2012-04-06 12:25:07 +09:00
|
|
|
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
|
2012-03-16 03:33:17 +09:00
|
|
|
}
|
2019-05-03 22:41:00 +09:00
|
|
|
#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
|
2011-11-28 15:37:32 +09:00
|
|
|
void invalidate_dcache_all(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
void flush_dcache_all(void)
|
|
|
|
{
|
|
|
|
}
|
2019-05-03 22:41:00 +09:00
|
|
|
#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
|
2012-02-07 02:12:10 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Stub implementations for l2 cache operations
|
|
|
|
*/
|
2015-10-24 01:06:40 +09:00
|
|
|
|
2014-10-28 04:10:06 +09:00
|
|
|
__weak void l2_cache_disable(void) {}
|
2015-10-24 01:06:40 +09:00
|
|
|
|
2017-03-18 22:01:44 +09:00
|
|
|
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
|
2015-10-24 01:06:40 +09:00
|
|
|
__weak void invalidate_l2_cache(void) {}
|
|
|
|
#endif
|
2018-08-17 03:23:11 +09:00
|
|
|
|
2019-05-03 22:41:00 +09:00
|
|
|
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
|
2018-08-17 03:23:11 +09:00
|
|
|
/* Invalidate entire I-cache and branch predictor array */
|
|
|
|
void invalidate_icache_all(void)
|
|
|
|
{
|
|
|
|
unsigned long i = 0;
|
|
|
|
|
|
|
|
asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
void invalidate_icache_all(void) {}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void enable_caches(void)
|
|
|
|
{
|
2019-05-03 22:41:00 +09:00
|
|
|
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
|
2018-08-17 03:23:11 +09:00
|
|
|
icache_enable();
|
|
|
|
#endif
|
2019-05-03 22:41:00 +09:00
|
|
|
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
|
2018-08-17 03:23:11 +09:00
|
|
|
dcache_enable();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|