2014-06-24 07:15:56 +09:00
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/*
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <fsl_ifc.h>
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#include <fsl_ddr.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <libfdt.h>
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2015-01-07 06:19:02 +09:00
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#include <fsl-mc/fsl_mc.h>
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2014-07-14 20:45:44 +09:00
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#include <environment.h>
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2015-10-26 20:47:50 +09:00
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#include <asm/arch/soc.h>
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2014-06-24 07:15:56 +09:00
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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init_final_memctl_regs();
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2014-07-14 20:45:44 +09:00
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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2014-06-24 07:15:56 +09:00
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return 0;
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}
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int board_early_init_f(void)
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{
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2015-03-21 11:28:12 +09:00
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fsl_lsch3_early_init_f();
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2014-06-24 07:15:56 +09:00
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return 0;
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}
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2014-08-14 02:21:05 +09:00
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
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print_ddr_info(0);
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2015-11-09 20:12:07 +09:00
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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2016-04-05 03:41:26 +09:00
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if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
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2014-08-14 02:21:05 +09:00
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puts("\nDP-DDR ");
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print_size(gd->bd->bi_dram[2].size, "");
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print_ddr_info(CONFIG_DP_DDR_CTRL);
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}
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2015-11-09 20:12:07 +09:00
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#endif
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2014-08-14 02:21:05 +09:00
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}
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2014-06-24 07:15:56 +09:00
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int dram_init(void)
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{
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gd->ram_size = initdram(0);
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return 0;
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}
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2015-03-20 01:20:43 +09:00
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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return 0;
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}
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#endif
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2014-06-24 07:15:56 +09:00
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int board_eth_init(bd_t *bis)
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{
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int error = 0;
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#ifdef CONFIG_SMC91111
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error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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#ifdef CONFIG_FSL_MC_ENET
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error = cpu_eth_init(bis);
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#endif
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return error;
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}
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#ifdef CONFIG_FSL_MC_ENET
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void fdt_fixup_board_enet(void *fdt)
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{
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int offset;
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2016-03-03 07:37:13 +09:00
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offset = fdt_path_offset(fdt, "/soc/fsl-mc");
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2015-01-07 06:19:02 +09:00
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/*
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* TODO: Remove this when backward compatibility
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2016-03-03 07:37:13 +09:00
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* with old DT node (/fsl-mc) is no longer needed.
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2015-01-07 06:19:02 +09:00
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*/
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if (offset < 0)
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2016-03-03 07:37:13 +09:00
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offset = fdt_path_offset(fdt, "/fsl-mc");
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2015-01-07 06:19:02 +09:00
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if (offset < 0) {
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printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
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__func__, offset);
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return;
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}
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2014-06-24 07:15:56 +09:00
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if (get_mc_boot_status() == 0)
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fdt_status_okay(fdt, offset);
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else
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fdt_status_fail(fdt, offset);
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}
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2016-11-17 09:02:57 +09:00
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void board_quiesce_devices(void)
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{
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fsl_mc_ldpaa_exit(gd->bd);
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}
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2014-06-24 07:15:56 +09:00
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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2014-10-24 09:58:47 +09:00
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int ft_board_setup(void *blob, bd_t *bd)
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2014-06-24 07:15:56 +09:00
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{
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2015-05-28 18:24:10 +09:00
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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2014-06-24 07:15:56 +09:00
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2014-09-09 04:20:01 +09:00
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ft_cpu_setup(blob, bd);
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2015-05-28 18:24:10 +09:00
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/* fixup DT for the two GPP DDR banks */
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base[0] = gd->bd->bi_dram[0].start;
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size[0] = gd->bd->bi_dram[0].size;
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base[1] = gd->bd->bi_dram[1].start;
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size[1] = gd->bd->bi_dram[1].size;
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2017-03-07 02:02:28 +09:00
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#ifdef CONFIG_RESV_RAM
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/* reduce size if reserved memory is within this bank */
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if (gd->arch.resv_ram >= base[0] &&
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gd->arch.resv_ram < base[0] + size[0])
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size[0] = gd->arch.resv_ram - base[0];
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else if (gd->arch.resv_ram >= base[1] &&
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gd->arch.resv_ram < base[1] + size[1])
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size[1] = gd->arch.resv_ram - base[1];
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#endif
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2015-05-28 18:24:10 +09:00
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fdt_fixup_memory_banks(blob, base, size, 2);
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2014-06-24 07:15:56 +09:00
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#ifdef CONFIG_FSL_MC_ENET
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fdt_fixup_board_enet(blob);
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#endif
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2014-10-24 09:58:47 +09:00
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return 0;
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2014-06-24 07:15:56 +09:00
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}
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#endif
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