2012-02-06 08:01:47 +09:00
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/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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2012-12-11 09:52:47 +09:00
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#include <fdtdec.h>
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2012-02-06 08:01:47 +09:00
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#include <asm/io.h>
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2012-07-24 06:23:55 +09:00
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#include <i2c.h>
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2012-02-06 08:01:47 +09:00
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#include <netdev.h>
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2012-11-02 10:15:37 +09:00
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#include <spi.h>
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2012-02-06 08:01:47 +09:00
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#include <asm/arch/cpu.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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2012-06-07 04:54:30 +09:00
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#include <asm/arch/pinmux.h>
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2012-02-06 08:01:47 +09:00
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#include <asm/arch/sromc.h>
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2012-12-10 10:55:48 +09:00
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#include <power/pmic.h>
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2012-02-06 08:01:47 +09:00
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
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2012-11-02 10:15:37 +09:00
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#ifdef CONFIG_EXYNOS_SPI
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spi_init();
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2012-08-24 09:39:24 +09:00
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#endif
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2012-02-06 08:01:47 +09:00
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
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+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
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+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
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+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
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+ get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
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+ get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
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+ get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
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+ get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
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return 0;
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}
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2012-12-10 10:55:48 +09:00
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#if defined(CONFIG_POWER)
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int power_init_board(void)
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{
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if (pmic_init(I2C_PMIC))
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return -1;
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else
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return 0;
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}
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#endif
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2012-02-06 08:01:47 +09:00
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
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PHYS_SDRAM_2_SIZE);
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
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gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
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PHYS_SDRAM_3_SIZE);
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
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gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
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PHYS_SDRAM_4_SIZE);
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gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
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gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
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PHYS_SDRAM_5_SIZE);
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gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
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gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
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PHYS_SDRAM_6_SIZE);
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gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
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gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
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PHYS_SDRAM_7_SIZE);
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gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
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gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
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PHYS_SDRAM_8_SIZE);
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}
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2012-12-11 09:52:47 +09:00
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#ifdef CONFIG_OF_CONTROL
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static int decode_sromc(const void *blob, struct fdt_sromc *config)
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{
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int err;
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int node;
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node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
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if (node < 0) {
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debug("Could not find SROMC node\n");
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return node;
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}
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config->bank = fdtdec_get_int(blob, node, "bank", 0);
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config->width = fdtdec_get_int(blob, node, "width", 2);
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err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
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FDT_SROM_TIMING_COUNT);
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if (err < 0) {
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debug("Could not decode SROMC configuration\n");
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return -FDT_ERR_NOTFOUND;
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}
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return 0;
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}
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#endif
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2012-02-09 10:26:19 +09:00
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SMC911X
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2012-12-11 09:52:47 +09:00
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u32 smc_bw_conf, smc_bc_conf;
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struct fdt_sromc config;
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fdt_addr_t base_addr;
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int node;
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#ifdef CONFIG_OF_CONTROL
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node = decode_sromc(gd->fdt_blob, &config);
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if (node < 0) {
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debug("%s: Could not find sromc configuration\n", __func__);
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return 0;
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}
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node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
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if (node < 0) {
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debug("%s: Could not find lan9215 configuration\n", __func__);
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return 0;
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}
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/* We now have a node, so any problems from now on are errors */
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base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
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if (base_addr == FDT_ADDR_T_NONE) {
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debug("%s: Could not find lan9215 address\n", __func__);
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2012-06-07 04:54:30 +09:00
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return -1;
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2012-12-11 09:52:47 +09:00
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}
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#else
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/* Non-FDT configuration - bank number and timing parameters*/
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config.bank = CONFIG_ENV_SROM_BANK;
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config.width = 2;
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config.timing[FDT_SROM_TACS] = 0x01;
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config.timing[FDT_SROM_TCOS] = 0x01;
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config.timing[FDT_SROM_TACC] = 0x06;
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config.timing[FDT_SROM_TCOH] = 0x01;
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config.timing[FDT_SROM_TAH] = 0x0C;
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config.timing[FDT_SROM_TACP] = 0x09;
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config.timing[FDT_SROM_PMC] = 0x01;
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base_addr = CONFIG_SMC911X_BASE;
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#endif
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/* Ethernet needs data bus width of 16 bits */
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if (config.width != 2) {
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debug("%s: Unsupported bus width %d\n", __func__,
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config.width);
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return -1;
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}
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smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
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| SROMC_BYTE_ENABLE(config.bank);
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smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
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SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
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SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
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SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
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SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
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SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
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SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
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/* Select and configure the SROMC bank */
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exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
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s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
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return smc911x_initialize(0, base_addr);
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2012-02-09 10:26:19 +09:00
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#endif
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return 0;
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}
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2012-02-06 08:01:47 +09:00
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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printf("\nBoard: SMDK5250\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_GENERIC_MMC
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int board_mmc_init(bd_t *bis)
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{
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2012-06-07 04:54:30 +09:00
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int err;
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2012-02-06 08:01:47 +09:00
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2012-07-04 05:03:00 +09:00
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err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
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2012-06-07 04:54:30 +09:00
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if (err) {
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2012-07-04 05:03:00 +09:00
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debug("SDMMC0 not configured\n");
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2012-06-07 04:54:30 +09:00
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return err;
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2012-02-06 08:01:47 +09:00
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}
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2012-07-04 05:03:00 +09:00
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err = s5p_mmc_init(0, 8);
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2012-02-06 08:01:47 +09:00
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return err;
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}
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#endif
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2012-06-07 04:54:30 +09:00
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static int board_uart_init(void)
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2012-02-06 08:01:47 +09:00
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{
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2012-06-07 04:54:30 +09:00
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int err;
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2012-02-06 08:01:47 +09:00
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2012-06-07 04:54:30 +09:00
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err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
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if (err) {
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debug("UART0 not configured\n");
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return err;
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2012-02-06 08:01:47 +09:00
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}
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2012-02-13 16:38:05 +09:00
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2012-06-07 04:54:30 +09:00
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err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
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if (err) {
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debug("UART1 not configured\n");
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return err;
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2012-02-13 16:38:05 +09:00
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}
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2012-06-07 04:54:30 +09:00
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err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
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if (err) {
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debug("UART2 not configured\n");
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return err;
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2012-02-13 16:38:05 +09:00
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}
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2012-06-07 04:54:30 +09:00
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err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
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if (err) {
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debug("UART3 not configured\n");
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return err;
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2012-02-13 16:38:05 +09:00
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}
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2012-06-07 04:54:30 +09:00
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return 0;
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2012-02-06 08:01:47 +09:00
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}
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2012-07-24 06:23:55 +09:00
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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static int board_i2c_init(void)
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{
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int i, err;
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for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
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err = exynos_pinmux_config((PERIPH_ID_I2C0 + i),
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PINMUX_FLAG_NONE);
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if (err) {
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debug("I2C%d not configured\n", (PERIPH_ID_I2C0 + i));
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return err;
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}
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}
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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return 0;
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}
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#endif
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2012-02-06 08:01:47 +09:00
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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2012-07-24 06:23:55 +09:00
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int err;
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err = board_uart_init();
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if (err) {
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debug("UART init failed\n");
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return err;
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}
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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err = board_i2c_init();
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#endif
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return err;
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2012-02-06 08:01:47 +09:00
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}
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#endif
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