mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-21 01:18:52 +09:00
229 lines
6.9 KiB
C
229 lines
6.9 KiB
C
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/*
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* DDR3 mem setup file for SMDK5250 board based on EXYNOS5
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*
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* Copyright (C) 2012 Samsung Electronics
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dmc.h>
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#include "setup.h"
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#include "clock_init.h"
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#define RDLVL_COMPLETE_TIMEOUT 10000
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static void reset_phy_ctrl(void)
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{
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struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
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writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
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writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
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}
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int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
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{
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unsigned int val;
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struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
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struct exynos5_dmc *dmc;
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int i;
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phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
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phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
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dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
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reset_phy_ctrl();
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/* Set Impedance Output Driver */
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val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
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(mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
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(mem->impedance << CA_CS_DRVR_DS_OFFSET) |
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(mem->impedance << CA_ADR_DRVR_DS_OFFSET);
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writel(val, &phy0_ctrl->phy_con39);
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writel(val, &phy1_ctrl->phy_con39);
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/* Set Read Latency and Burst Length for PHY0 and PHY1 */
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val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
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(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
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writel(val, &phy0_ctrl->phy_con42);
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writel(val, &phy1_ctrl->phy_con42);
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/* ZQ Calibration */
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if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl))
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return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
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/* DQ Signal */
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writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
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writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
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writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
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| (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
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&dmc->concontrol);
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update_reset_dll(dmc, DDR_MODE_DDR3);
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/* DQS Signal */
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writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
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writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
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writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
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writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
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writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
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writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
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val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
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(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
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(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
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(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
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writel(val, &phy0_ctrl->phy_con12);
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writel(val, &phy1_ctrl->phy_con12);
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/* Start DLL locking */
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writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
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&phy0_ctrl->phy_con12);
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writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
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&phy1_ctrl->phy_con12);
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update_reset_dll(dmc, DDR_MODE_DDR3);
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writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
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&dmc->concontrol);
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/* Memory Channel Inteleaving Size */
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writel(mem->iv_size, &dmc->ivcontrol);
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writel(mem->memconfig, &dmc->memconfig0);
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writel(mem->memconfig, &dmc->memconfig1);
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writel(mem->membaseconfig0, &dmc->membaseconfig0);
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writel(mem->membaseconfig1, &dmc->membaseconfig1);
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/* Precharge Configuration */
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writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
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&dmc->prechconfig);
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/* Power Down mode Configuration */
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writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
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mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
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&dmc->pwrdnconfig);
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/* TimingRow, TimingData, TimingPower and Timingaref
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* values as per Memory AC parameters
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*/
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writel(mem->timing_ref, &dmc->timingref);
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writel(mem->timing_row, &dmc->timingrow);
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writel(mem->timing_data, &dmc->timingdata);
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writel(mem->timing_power, &dmc->timingpower);
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/* Send PALL command */
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dmc_config_prech(mem, dmc);
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/* Send NOP, MRS and ZQINIT commands */
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dmc_config_mrs(mem, dmc);
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if (mem->gate_leveling_enable) {
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val = PHY_CON0_RESET_VAL;
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val |= P0_CMD_EN;
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writel(val, &phy0_ctrl->phy_con0);
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writel(val, &phy1_ctrl->phy_con0);
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val = PHY_CON2_RESET_VAL;
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val |= INIT_DESKEW_EN;
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writel(val, &phy0_ctrl->phy_con2);
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writel(val, &phy1_ctrl->phy_con2);
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val = PHY_CON0_RESET_VAL;
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val |= P0_CMD_EN;
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val |= BYTE_RDLVL_EN;
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writel(val, &phy0_ctrl->phy_con0);
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writel(val, &phy1_ctrl->phy_con0);
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val = (mem->ctrl_start_point <<
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PHY_CON12_CTRL_START_POINT_SHIFT) |
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(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
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(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
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(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
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(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
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writel(val, &phy0_ctrl->phy_con12);
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writel(val, &phy1_ctrl->phy_con12);
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val = PHY_CON2_RESET_VAL;
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val |= INIT_DESKEW_EN;
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val |= RDLVL_GATE_EN;
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writel(val, &phy0_ctrl->phy_con2);
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writel(val, &phy1_ctrl->phy_con2);
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val = PHY_CON0_RESET_VAL;
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val |= P0_CMD_EN;
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val |= BYTE_RDLVL_EN;
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val |= CTRL_SHGATE;
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writel(val, &phy0_ctrl->phy_con0);
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writel(val, &phy1_ctrl->phy_con0);
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val = PHY_CON1_RESET_VAL;
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val &= ~(CTRL_GATEDURADJ_MASK);
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writel(val, &phy0_ctrl->phy_con1);
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writel(val, &phy1_ctrl->phy_con1);
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writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
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i = RDLVL_COMPLETE_TIMEOUT;
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while ((readl(&dmc->phystatus) &
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(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
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(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
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/*
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* TODO(waihong): Comment on how long this take to
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* timeout
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*/
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sdelay(100);
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i--;
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}
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if (!i)
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return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
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writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
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writel(0, &phy0_ctrl->phy_con14);
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writel(0, &phy1_ctrl->phy_con14);
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val = (mem->ctrl_start_point <<
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PHY_CON12_CTRL_START_POINT_SHIFT) |
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(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
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(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
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(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
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(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
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(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
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writel(val, &phy0_ctrl->phy_con12);
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writel(val, &phy1_ctrl->phy_con12);
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update_reset_dll(dmc, DDR_MODE_DDR3);
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}
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/* Send PALL command */
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dmc_config_prech(mem, dmc);
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writel(mem->memcontrol, &dmc->memcontrol);
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/* Set DMC Concontrol and enable auto-refresh counter */
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writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
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| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
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return 0;
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}
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