2009-07-22 00:32:21 +09:00
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/*
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* (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
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* (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
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* (C) Copyright 2008 Armadeus Systems nc
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* (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include "fec_mxc.h"
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_MII
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#error "CONFIG_MII has to be defined!"
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#endif
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#undef DEBUG
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struct nbuf {
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uint8_t data[1500]; /**< actual data */
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int length; /**< actual length */
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int used; /**< buffer in use or not */
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uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
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};
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struct fec_priv gfec = {
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.eth = (struct ethernet_regs *)IMX_FEC_BASE,
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.xcv_type = MII100,
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.rbd_base = NULL,
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.rbd_index = 0,
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.tbd_base = NULL,
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.tbd_index = 0,
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.bd = NULL,
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2009-10-29 16:22:43 +09:00
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.rdb_ptr = NULL,
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.base_ptr = NULL,
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2009-07-22 00:32:21 +09:00
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};
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/*
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* MII-interface related functions
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*/
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static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
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uint16_t *retVal)
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{
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struct eth_device *edev = eth_get_dev_by_name(dev);
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struct fec_priv *fec = (struct fec_priv *)edev->priv;
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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uint32_t start;
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/*
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* reading from any PHY's register is done by properly
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* programming the FEC's MII data register.
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*/
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writel(FEC_IEVENT_MII, &fec->eth->ievent);
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
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phy | reg, &fec->eth->mii_data);
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/*
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* wait for the related interrupt
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*/
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start = get_timer_masked();
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while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
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if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
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printf("Read MDIO failed...\n");
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return -1;
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}
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}
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/*
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* clear mii interrupt bit
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*/
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writel(FEC_IEVENT_MII, &fec->eth->ievent);
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/*
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* it's now safe to read the PHY's register
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*/
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*retVal = readl(&fec->eth->mii_data);
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debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
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regAddr, *retVal);
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return 0;
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}
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2010-02-01 22:51:30 +09:00
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static void fec_mii_setspeed(struct fec_priv *fec)
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{
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/*
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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
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* and do not drop the Preamble.
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*/
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writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
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&fec->eth->mii_speed);
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debug("fec_init: mii_speed %#lx\n",
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fec->eth->mii_speed);
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}
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2009-07-22 00:32:21 +09:00
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static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
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uint16_t data)
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{
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struct eth_device *edev = eth_get_dev_by_name(dev);
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struct fec_priv *fec = (struct fec_priv *)edev->priv;
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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uint32_t start;
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
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FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
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/*
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* wait for the MII interrupt
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*/
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start = get_timer_masked();
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while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
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if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
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printf("Write MDIO failed...\n");
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return -1;
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}
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}
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/*
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* clear MII interrupt bit
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*/
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writel(FEC_IEVENT_MII, &fec->eth->ievent);
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debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
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regAddr, data);
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return 0;
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}
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static int miiphy_restart_aneg(struct eth_device *dev)
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{
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/*
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* Wake up from sleep if necessary
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* Reset PHY, then delay 300ns
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*/
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2010-01-26 15:12:55 +09:00
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#ifdef CONFIG_MX27
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2009-07-22 00:32:21 +09:00
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miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
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2010-01-26 15:12:55 +09:00
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#endif
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2009-07-22 00:32:21 +09:00
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miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
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PHY_BMCR_RESET);
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udelay(1000);
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/*
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* Set the auto-negotiation advertisement register bits
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*/
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2009-10-29 16:18:34 +09:00
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miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR,
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PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
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PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3);
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2009-07-22 00:32:21 +09:00
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miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
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PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
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return 0;
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}
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static int miiphy_wait_aneg(struct eth_device *dev)
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{
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uint32_t start;
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uint16_t status;
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/*
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* Wait for AN completion
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*/
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start = get_timer_masked();
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do {
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if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
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printf("%s: Autonegotiation timeout\n", dev->name);
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return -1;
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}
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if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR,
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PHY_BMSR, &status)) {
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printf("%s: Autonegotiation failed. status: 0x%04x\n",
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dev->name, status);
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return -1;
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}
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} while (!(status & PHY_BMSR_LS));
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return 0;
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}
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static int fec_rx_task_enable(struct fec_priv *fec)
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{
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writel(1 << 24, &fec->eth->r_des_active);
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return 0;
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}
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static int fec_rx_task_disable(struct fec_priv *fec)
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{
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return 0;
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}
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static int fec_tx_task_enable(struct fec_priv *fec)
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{
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writel(1 << 24, &fec->eth->x_des_active);
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return 0;
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}
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static int fec_tx_task_disable(struct fec_priv *fec)
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{
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return 0;
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}
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/**
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* Initialize receive task's buffer descriptors
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* @param[in] fec all we know about the device yet
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* @param[in] count receive buffer count to be allocated
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* @param[in] size size of each receive buffer
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* @return 0 on success
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*
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* For this task we need additional memory for the data buffers. And each
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* data buffer requires some alignment. Thy must be aligned to a specific
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* boundary each (DB_DATA_ALIGNMENT).
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*/
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static int fec_rbd_init(struct fec_priv *fec, int count, int size)
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{
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int ix;
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uint32_t p = 0;
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/* reserve data memory and consider alignment */
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2009-10-29 16:22:43 +09:00
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if (fec->rdb_ptr == NULL)
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fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
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2009-07-22 00:32:21 +09:00
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p = (uint32_t)fec->rdb_ptr;
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if (!p) {
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2010-02-01 22:51:30 +09:00
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puts("fec_mxc: not enough malloc memory\n");
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2009-07-22 00:32:21 +09:00
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return -ENOMEM;
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}
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memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
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p += DB_DATA_ALIGNMENT-1;
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p &= ~(DB_DATA_ALIGNMENT-1);
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for (ix = 0; ix < count; ix++) {
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writel(p, &fec->rbd_base[ix].data_pointer);
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p += size;
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writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
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writew(0, &fec->rbd_base[ix].data_length);
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}
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/*
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* mark the last RBD to close the ring
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*/
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writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
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fec->rbd_index = 0;
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return 0;
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}
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/**
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* Initialize transmit task's buffer descriptors
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* @param[in] fec all we know about the device yet
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*
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* Transmit buffers are created externally. We only have to init the BDs here.\n
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* Note: There is a race condition in the hardware. When only one BD is in
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* use it must be marked with the WRAP bit to use it for every transmitt.
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* This bit in combination with the READY bit results into double transmit
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* of each data buffer. It seems the state machine checks READY earlier then
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* resetting it after the first transfer.
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* Using two BDs solves this issue.
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*/
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static void fec_tbd_init(struct fec_priv *fec)
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{
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writew(0x0000, &fec->tbd_base[0].status);
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writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
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fec->tbd_index = 0;
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}
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/**
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* Mark the given read buffer descriptor as free
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* @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
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* @param[in] pRbd buffer descriptor to mark free again
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*/
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static void fec_rbd_clean(int last, struct fec_bd *pRbd)
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{
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/*
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* Reset buffer descriptor as empty
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*/
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if (last)
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writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
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else
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writew(FEC_RBD_EMPTY, &pRbd->status);
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/*
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* no data in it
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*/
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writew(0, &pRbd->data_length);
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}
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static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
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{
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2010-02-01 22:51:30 +09:00
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/*
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* The MX27 can store the mac address in internal eeprom
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* This mechanism is not supported now by MX51
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*/
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#ifdef CONFIG_MX51
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return -1;
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#else
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2009-07-22 00:32:21 +09:00
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struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
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int i;
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for (i = 0; i < 6; i++)
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mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]);
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return is_valid_ether_addr(mac);
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2010-02-01 22:51:30 +09:00
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#endif
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2009-07-22 00:32:21 +09:00
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}
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2010-02-01 22:51:30 +09:00
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static int fec_set_hwaddr(struct eth_device *dev)
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2009-07-22 00:32:21 +09:00
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{
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2010-02-01 22:51:30 +09:00
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uchar *mac = dev->enetaddr;
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2009-07-22 00:32:21 +09:00
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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writel(0, &fec->eth->iaddr1);
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writel(0, &fec->eth->iaddr2);
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writel(0, &fec->eth->gaddr1);
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writel(0, &fec->eth->gaddr2);
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/*
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* Set physical address
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*/
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writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
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|
|
&fec->eth->paddr1);
|
|
|
|
writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Start the FEC engine
|
|
|
|
* @param[in] dev Our device to handle
|
|
|
|
*/
|
|
|
|
static int fec_open(struct eth_device *edev)
|
|
|
|
{
|
|
|
|
struct fec_priv *fec = (struct fec_priv *)edev->priv;
|
|
|
|
|
|
|
|
debug("fec_open: fec_open(dev)\n");
|
|
|
|
/* full-duplex, heartbeat disabled */
|
|
|
|
writel(1 << 2, &fec->eth->x_cntrl);
|
|
|
|
fec->rbd_index = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable FEC-Lite controller
|
|
|
|
*/
|
2010-01-26 15:12:55 +09:00
|
|
|
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
|
|
|
|
&fec->eth->ecntrl);
|
2010-01-26 15:12:57 +09:00
|
|
|
#ifdef CONFIG_MX25
|
|
|
|
udelay(100);
|
|
|
|
/*
|
|
|
|
* setup the MII gasket for RMII mode
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* disable the gasket */
|
|
|
|
writew(0, &fec->eth->miigsk_enr);
|
|
|
|
|
|
|
|
/* wait for the gasket to be disabled */
|
|
|
|
while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
|
|
|
|
udelay(2);
|
|
|
|
|
|
|
|
/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
|
|
|
|
writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
|
|
|
|
|
|
|
|
/* re-enable the gasket */
|
|
|
|
writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
|
|
|
|
|
|
|
|
/* wait until MII gasket is ready */
|
|
|
|
int max_loops = 10;
|
|
|
|
while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
|
|
|
|
if (--max_loops <= 0) {
|
|
|
|
printf("WAIT for MII Gasket ready timed out\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
2009-07-22 00:32:21 +09:00
|
|
|
|
|
|
|
miiphy_wait_aneg(edev);
|
2009-10-29 16:18:34 +09:00
|
|
|
miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
|
|
|
|
miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR);
|
2009-07-22 00:32:21 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable SmartDMA receive task
|
|
|
|
*/
|
|
|
|
fec_rx_task_enable(fec);
|
|
|
|
|
|
|
|
udelay(100000);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fec_init(struct eth_device *dev, bd_t* bd)
|
|
|
|
{
|
|
|
|
uint32_t base;
|
|
|
|
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* reserve memory for both buffer descriptor chains at once
|
|
|
|
* Datasheet forces the startaddress of each chain is 16 byte
|
|
|
|
* aligned
|
|
|
|
*/
|
2009-10-29 16:22:43 +09:00
|
|
|
if (fec->base_ptr == NULL)
|
|
|
|
fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
|
|
|
|
sizeof(struct fec_bd) + DB_ALIGNMENT);
|
2009-07-22 00:32:21 +09:00
|
|
|
base = (uint32_t)fec->base_ptr;
|
|
|
|
if (!base) {
|
2010-02-01 22:51:30 +09:00
|
|
|
puts("fec_mxc: not enough malloc memory\n");
|
2009-07-22 00:32:21 +09:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
memset((void *)base, 0, (2 + FEC_RBD_NUM) *
|
|
|
|
sizeof(struct fec_bd) + DB_ALIGNMENT);
|
|
|
|
base += (DB_ALIGNMENT-1);
|
|
|
|
base &= ~(DB_ALIGNMENT-1);
|
|
|
|
|
|
|
|
fec->rbd_base = (struct fec_bd *)base;
|
|
|
|
|
|
|
|
base += FEC_RBD_NUM * sizeof(struct fec_bd);
|
|
|
|
|
|
|
|
fec->tbd_base = (struct fec_bd *)base;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set interrupt mask register
|
|
|
|
*/
|
|
|
|
writel(0x00000000, &fec->eth->imask);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear FEC-Lite interrupt event register(IEVENT)
|
|
|
|
*/
|
|
|
|
writel(0xffffffff, &fec->eth->ievent);
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set FEC-Lite receive control register(R_CNTRL):
|
|
|
|
*/
|
|
|
|
if (fec->xcv_type == SEVENWIRE) {
|
|
|
|
/*
|
|
|
|
* Frame length=1518; 7-wire mode
|
|
|
|
*/
|
|
|
|
writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Frame length=1518; MII mode;
|
|
|
|
*/
|
|
|
|
writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
|
2010-02-01 22:51:30 +09:00
|
|
|
|
|
|
|
fec_mii_setspeed(fec);
|
2009-07-22 00:32:21 +09:00
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Set Opcode/Pause Duration Register
|
|
|
|
*/
|
|
|
|
writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
|
|
|
|
writel(0x2, &fec->eth->x_wmrk);
|
|
|
|
/*
|
|
|
|
* Set multicast address filter
|
|
|
|
*/
|
|
|
|
writel(0x00000000, &fec->eth->gaddr1);
|
|
|
|
writel(0x00000000, &fec->eth->gaddr2);
|
|
|
|
|
|
|
|
|
|
|
|
/* clear MIB RAM */
|
|
|
|
long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200);
|
|
|
|
while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC))
|
|
|
|
*mib_ptr++ = 0;
|
|
|
|
|
|
|
|
/* FIFO receive start register */
|
|
|
|
writel(0x520, &fec->eth->r_fstart);
|
|
|
|
|
|
|
|
/* size and address of each buffer */
|
|
|
|
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
|
|
|
|
writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
|
|
|
|
writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize RxBD/TxBD rings
|
|
|
|
*/
|
|
|
|
if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
|
|
|
|
free(fec->base_ptr);
|
2009-12-11 17:47:28 +09:00
|
|
|
fec->base_ptr = NULL;
|
2009-07-22 00:32:21 +09:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
fec_tbd_init(fec);
|
|
|
|
|
|
|
|
|
|
|
|
if (fec->xcv_type != SEVENWIRE)
|
|
|
|
miiphy_restart_aneg(dev);
|
|
|
|
|
|
|
|
fec_open(dev);
|
2010-02-01 22:51:30 +09:00
|
|
|
fec_set_hwaddr(dev);
|
2009-07-22 00:32:21 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Halt the FEC engine
|
|
|
|
* @param[in] dev Our device to handle
|
|
|
|
*/
|
|
|
|
static void fec_halt(struct eth_device *dev)
|
|
|
|
{
|
|
|
|
struct fec_priv *fec = &gfec;
|
|
|
|
int counter = 0xffff;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* issue graceful stop command to the FEC transmitter if necessary
|
|
|
|
*/
|
2010-01-26 15:12:55 +09:00
|
|
|
writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
|
2009-07-22 00:32:21 +09:00
|
|
|
&fec->eth->x_cntrl);
|
|
|
|
|
|
|
|
debug("eth_halt: wait for stop regs\n");
|
|
|
|
/*
|
|
|
|
* wait for graceful stop to register
|
|
|
|
*/
|
|
|
|
while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
|
2010-01-26 15:12:55 +09:00
|
|
|
udelay(1);
|
2009-07-22 00:32:21 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable SmartDMA tasks
|
|
|
|
*/
|
|
|
|
fec_tx_task_disable(fec);
|
|
|
|
fec_rx_task_disable(fec);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable the Ethernet Controller
|
|
|
|
* Note: this will also reset the BD index counter!
|
|
|
|
*/
|
2010-01-26 15:12:57 +09:00
|
|
|
writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
|
|
|
|
&fec->eth->ecntrl);
|
2009-07-22 00:32:21 +09:00
|
|
|
fec->rbd_index = 0;
|
|
|
|
fec->tbd_index = 0;
|
|
|
|
debug("eth_halt: done\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Transmit one frame
|
|
|
|
* @param[in] dev Our ethernet device to handle
|
|
|
|
* @param[in] packet Pointer to the data to be transmitted
|
|
|
|
* @param[in] length Data count in bytes
|
|
|
|
* @return 0 on success
|
|
|
|
*/
|
|
|
|
static int fec_send(struct eth_device *dev, volatile void* packet, int length)
|
|
|
|
{
|
|
|
|
unsigned int status;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This routine transmits one frame. This routine only accepts
|
|
|
|
* 6-byte Ethernet addresses.
|
|
|
|
*/
|
|
|
|
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check for valid length of data.
|
|
|
|
*/
|
|
|
|
if ((length > 1500) || (length <= 0)) {
|
2010-02-01 22:51:30 +09:00
|
|
|
printf("Payload (%d) too large\n", length);
|
2009-07-22 00:32:21 +09:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup the transmit buffer
|
|
|
|
* Note: We are always using the first buffer for transmission,
|
|
|
|
* the second will be empty and only used to stop the DMA engine
|
|
|
|
*/
|
|
|
|
writew(length, &fec->tbd_base[fec->tbd_index].data_length);
|
|
|
|
writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
|
|
|
|
/*
|
|
|
|
* update BD's status now
|
|
|
|
* This block:
|
|
|
|
* - is always the last in a chain (means no chain)
|
|
|
|
* - should transmitt the CRC
|
|
|
|
* - might be the last BD in the list, so the address counter should
|
|
|
|
* wrap (-> keep the WRAP flag)
|
|
|
|
*/
|
|
|
|
status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
|
|
|
|
status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
|
|
|
|
writew(status, &fec->tbd_base[fec->tbd_index].status);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable SmartDMA transmit task
|
|
|
|
*/
|
|
|
|
fec_tx_task_enable(fec);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* wait until frame is sent .
|
|
|
|
*/
|
|
|
|
while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
|
2010-01-26 15:12:55 +09:00
|
|
|
udelay(1);
|
2009-07-22 00:32:21 +09:00
|
|
|
}
|
|
|
|
debug("fec_send: status 0x%x index %d\n",
|
|
|
|
readw(&fec->tbd_base[fec->tbd_index].status),
|
|
|
|
fec->tbd_index);
|
|
|
|
/* for next transmission use the other buffer */
|
|
|
|
if (fec->tbd_index)
|
|
|
|
fec->tbd_index = 0;
|
|
|
|
else
|
|
|
|
fec->tbd_index = 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Pull one frame from the card
|
|
|
|
* @param[in] dev Our ethernet device to handle
|
|
|
|
* @return Length of packet read
|
|
|
|
*/
|
|
|
|
static int fec_recv(struct eth_device *dev)
|
|
|
|
{
|
|
|
|
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
|
|
|
struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
|
|
|
|
unsigned long ievent;
|
|
|
|
int frame_length, len = 0;
|
|
|
|
struct nbuf *frame;
|
|
|
|
uint16_t bd_status;
|
|
|
|
uchar buff[FEC_MAX_PKT_SIZE];
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if any critical events have happened
|
|
|
|
*/
|
|
|
|
ievent = readl(&fec->eth->ievent);
|
|
|
|
writel(ievent, &fec->eth->ievent);
|
|
|
|
debug("fec_recv: ievent 0x%x\n", ievent);
|
|
|
|
if (ievent & FEC_IEVENT_BABR) {
|
|
|
|
fec_halt(dev);
|
|
|
|
fec_init(dev, fec->bd);
|
|
|
|
printf("some error: 0x%08lx\n", ievent);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if (ievent & FEC_IEVENT_HBERR) {
|
|
|
|
/* Heartbeat error */
|
|
|
|
writel(0x00000001 | readl(&fec->eth->x_cntrl),
|
|
|
|
&fec->eth->x_cntrl);
|
|
|
|
}
|
|
|
|
if (ievent & FEC_IEVENT_GRA) {
|
|
|
|
/* Graceful stop complete */
|
|
|
|
if (readl(&fec->eth->x_cntrl) & 0x00000001) {
|
|
|
|
fec_halt(dev);
|
|
|
|
writel(~0x00000001 & readl(&fec->eth->x_cntrl),
|
|
|
|
&fec->eth->x_cntrl);
|
|
|
|
fec_init(dev, fec->bd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ensure reading the right buffer status
|
|
|
|
*/
|
|
|
|
bd_status = readw(&rbd->status);
|
|
|
|
debug("fec_recv: status 0x%x\n", bd_status);
|
|
|
|
|
|
|
|
if (!(bd_status & FEC_RBD_EMPTY)) {
|
|
|
|
if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
|
|
|
|
((readw(&rbd->data_length) - 4) > 14)) {
|
|
|
|
/*
|
|
|
|
* Get buffer address and size
|
|
|
|
*/
|
|
|
|
frame = (struct nbuf *)readl(&rbd->data_pointer);
|
|
|
|
frame_length = readw(&rbd->data_length) - 4;
|
|
|
|
/*
|
|
|
|
* Fill the buffer and pass it to upper layers
|
|
|
|
*/
|
|
|
|
memcpy(buff, frame->data, frame_length);
|
|
|
|
NetReceive(buff, frame_length);
|
|
|
|
len = frame_length;
|
|
|
|
} else {
|
|
|
|
if (bd_status & FEC_RBD_ERR)
|
|
|
|
printf("error frame: 0x%08lx 0x%08x\n",
|
|
|
|
(ulong)rbd->data_pointer,
|
|
|
|
bd_status);
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* free the current buffer, restart the engine
|
|
|
|
* and move forward to the next buffer
|
|
|
|
*/
|
|
|
|
fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
|
|
|
|
fec_rx_task_enable(fec);
|
|
|
|
fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
|
|
|
|
}
|
|
|
|
debug("fec_recv: stop\n");
|
|
|
|
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fec_probe(bd_t *bd)
|
|
|
|
{
|
|
|
|
struct eth_device *edev;
|
|
|
|
struct fec_priv *fec = &gfec;
|
|
|
|
unsigned char ethaddr[6];
|
|
|
|
|
|
|
|
/* create and fill edev struct */
|
|
|
|
edev = (struct eth_device *)malloc(sizeof(struct eth_device));
|
|
|
|
if (!edev) {
|
2010-02-01 22:51:30 +09:00
|
|
|
puts("fec_mxc: not enough malloc memory\n");
|
2009-07-22 00:32:21 +09:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
edev->priv = fec;
|
|
|
|
edev->init = fec_init;
|
|
|
|
edev->send = fec_send;
|
|
|
|
edev->recv = fec_recv;
|
|
|
|
edev->halt = fec_halt;
|
|
|
|
|
|
|
|
fec->eth = (struct ethernet_regs *)IMX_FEC_BASE;
|
|
|
|
fec->bd = bd;
|
|
|
|
|
|
|
|
fec->xcv_type = MII100;
|
|
|
|
|
|
|
|
/* Reset chip. */
|
2010-01-26 15:12:55 +09:00
|
|
|
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
|
2009-07-22 00:32:21 +09:00
|
|
|
while (readl(&fec->eth->ecntrl) & 1)
|
|
|
|
udelay(10);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set interrupt mask register
|
|
|
|
*/
|
|
|
|
writel(0x00000000, &fec->eth->imask);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear FEC-Lite interrupt event register(IEVENT)
|
|
|
|
*/
|
|
|
|
writel(0xffffffff, &fec->eth->ievent);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set FEC-Lite receive control register(R_CNTRL):
|
|
|
|
*/
|
|
|
|
/*
|
|
|
|
* Frame length=1518; MII mode;
|
|
|
|
*/
|
|
|
|
writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
|
2010-02-01 22:51:30 +09:00
|
|
|
fec_mii_setspeed(fec);
|
2009-07-22 00:32:21 +09:00
|
|
|
|
|
|
|
sprintf(edev->name, "FEC_MXC");
|
|
|
|
|
|
|
|
miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
|
|
|
|
|
|
|
|
eth_register(edev);
|
|
|
|
|
2010-02-01 22:51:30 +09:00
|
|
|
if (fec_get_hwaddr(edev, ethaddr) == 0) {
|
2009-07-22 00:32:21 +09:00
|
|
|
printf("got MAC address from EEPROM: %pM\n", ethaddr);
|
2010-02-01 22:51:30 +09:00
|
|
|
memcpy(edev->enetaddr, ethaddr, 6);
|
2009-07-22 00:32:21 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int fecmxc_initialize(bd_t *bd)
|
|
|
|
{
|
|
|
|
int lout = 1;
|
|
|
|
|
|
|
|
debug("eth_init: fec_probe(bd)\n");
|
|
|
|
lout = fec_probe(bd);
|
|
|
|
|
|
|
|
return lout;
|
|
|
|
}
|