mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-29 05:18:51 +09:00
504 lines
13 KiB
C
504 lines
13 KiB
C
![]() |
/*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Aaron <leafy.myeh@allwinnertech.com>
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*
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* MMC driver for allwinner sunxi platform.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/mmc.h>
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struct sunxi_mmc_des {
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u32 reserved1_1:1;
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u32 dic:1; /* disable interrupt on completion */
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u32 last_des:1; /* 1-this data buffer is the last buffer */
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u32 first_des:1; /* 1-data buffer is the first buffer,
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0-data buffer contained in the next
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descriptor is 1st buffer */
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u32 des_chain:1; /* 1-the 2nd address in the descriptor is the
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next descriptor address */
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u32 end_of_ring:1; /* 1-last descriptor flag when using dual
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data buffer in descriptor */
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u32 reserved1_2:24;
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u32 card_err_sum:1; /* transfer error flag */
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u32 own:1; /* des owner:1-idma owns it, 0-host owns it */
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#define SDXC_DES_NUM_SHIFT 16
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#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
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u32 data_buf1_sz:16;
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u32 data_buf2_sz:16;
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u32 buf_addr_ptr1;
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u32 buf_addr_ptr2;
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};
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struct sunxi_mmc_host {
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unsigned mmc_no;
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uint32_t *mclkreg;
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unsigned database;
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unsigned fatal_err;
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unsigned mod_clk;
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struct sunxi_mmc *reg;
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struct mmc_config cfg;
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};
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/* support 4 mmc hosts */
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struct sunxi_mmc_host mmc_host[4];
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static int mmc_resource_init(int sdc_no)
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{
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struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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debug("init mmc %d resource\n", sdc_no);
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switch (sdc_no) {
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case 0:
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mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
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mmchost->mclkreg = &ccm->sd0_clk_cfg;
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break;
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case 1:
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mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
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mmchost->mclkreg = &ccm->sd1_clk_cfg;
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break;
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case 2:
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mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
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mmchost->mclkreg = &ccm->sd2_clk_cfg;
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break;
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case 3:
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mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
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mmchost->mclkreg = &ccm->sd3_clk_cfg;
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break;
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default:
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printf("Wrong mmc number %d\n", sdc_no);
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return -1;
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}
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mmchost->database = (unsigned int)mmchost->reg + 0x100;
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mmchost->mmc_no = sdc_no;
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return 0;
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}
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static int mmc_clk_io_on(int sdc_no)
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{
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unsigned int pll_clk;
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unsigned int divider;
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struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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debug("init mmc %d clock and io\n", sdc_no);
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/* config ahb clock */
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setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
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/* config mod clock */
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pll_clk = clock_get_pll6();
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/* should be close to 100 MHz but no more, so round up */
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divider = ((pll_clk + 99999999) / 100000000) - 1;
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writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider,
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mmchost->mclkreg);
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mmchost->mod_clk = pll_clk / (divider + 1);
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return 0;
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}
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static int mmc_update_clk(struct mmc *mmc)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned int cmd;
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unsigned timeout_msecs = 2000;
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cmd = SUNXI_MMC_CMD_START |
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SUNXI_MMC_CMD_UPCLK_ONLY |
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SUNXI_MMC_CMD_WAIT_PRE_OVER;
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writel(cmd, &mmchost->reg->cmd);
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while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
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if (!timeout_msecs--)
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return -1;
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udelay(1000);
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}
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/* clock update sets various irq status bits, clear these */
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writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
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return 0;
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}
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static int mmc_config_clock(struct mmc *mmc, unsigned div)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned rval = readl(&mmchost->reg->clkcr);
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/* Disable Clock */
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rval &= ~SUNXI_MMC_CLK_ENABLE;
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writel(rval, &mmchost->reg->clkcr);
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if (mmc_update_clk(mmc))
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return -1;
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/* Change Divider Factor */
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rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
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rval |= div;
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writel(rval, &mmchost->reg->clkcr);
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if (mmc_update_clk(mmc))
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return -1;
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/* Re-enable Clock */
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rval |= SUNXI_MMC_CLK_ENABLE;
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writel(rval, &mmchost->reg->clkcr);
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if (mmc_update_clk(mmc))
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return -1;
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return 0;
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}
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static void mmc_set_ios(struct mmc *mmc)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned int clkdiv = 0;
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debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n",
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mmc->bus_width, mmc->clock, mmchost->mod_clk);
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/* Change clock first */
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clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2;
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if (mmc->clock) {
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if (mmc_config_clock(mmc, clkdiv)) {
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mmchost->fatal_err = 1;
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return;
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}
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}
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/* Change bus width */
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if (mmc->bus_width == 8)
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writel(0x2, &mmchost->reg->width);
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else if (mmc->bus_width == 4)
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writel(0x1, &mmchost->reg->width);
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else
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writel(0x0, &mmchost->reg->width);
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}
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static int mmc_core_init(struct mmc *mmc)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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/* Reset controller */
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writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
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return 0;
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}
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static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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const int reading = !!(data->flags & MMC_DATA_READ);
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const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
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SUNXI_MMC_STATUS_FIFO_FULL;
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unsigned i;
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unsigned byte_cnt = data->blocksize * data->blocks;
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unsigned timeout_msecs = 2000;
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unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
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for (i = 0; i < (byte_cnt >> 2); i++) {
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while (readl(&mmchost->reg->status) & status_bit) {
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if (!timeout_msecs--)
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return -1;
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udelay(1000);
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}
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if (reading)
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buff[i] = readl(mmchost->database);
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else
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writel(buff[i], mmchost->database);
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}
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return 0;
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}
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static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned byte_cnt = data->blocksize * data->blocks;
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unsigned char *buff;
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unsigned des_idx = 0;
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unsigned buff_frag_num =
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(byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT;
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unsigned remain;
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unsigned i, rval;
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ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num);
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buff = data->flags & MMC_DATA_READ ?
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(unsigned char *)data->dest : (unsigned char *)data->src;
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remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1);
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flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
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for (i = 0; i < buff_frag_num; i++, des_idx++) {
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memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des));
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pdes[des_idx].des_chain = 1;
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pdes[des_idx].own = 1;
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pdes[des_idx].dic = 1;
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if (buff_frag_num > 1 && i != buff_frag_num - 1)
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pdes[des_idx].data_buf1_sz = 0; /* 0 == max_len */
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else
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pdes[des_idx].data_buf1_sz = remain;
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pdes[des_idx].buf_addr_ptr1 =
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(u32) buff + i * SDXC_DES_BUFFER_MAX_LEN;
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if (i == 0)
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pdes[des_idx].first_des = 1;
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if (i == buff_frag_num - 1) {
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pdes[des_idx].dic = 0;
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pdes[des_idx].last_des = 1;
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pdes[des_idx].end_of_ring = 1;
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pdes[des_idx].buf_addr_ptr2 = 0;
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} else {
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pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1];
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}
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}
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flush_cache((unsigned long)pdes,
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sizeof(struct sunxi_mmc_des) * (des_idx + 1));
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rval = readl(&mmchost->reg->gctrl);
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/* Enable DMA */
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writel(rval | SUNXI_MMC_GCTRL_DMA_RESET | SUNXI_MMC_GCTRL_DMA_ENABLE,
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&mmchost->reg->gctrl);
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/* Reset iDMA */
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writel(SUNXI_MMC_IDMAC_RESET, &mmchost->reg->dmac);
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/* Enable iDMA */
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writel(SUNXI_MMC_IDMAC_FIXBURST | SUNXI_MMC_IDMAC_ENABLE,
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&mmchost->reg->dmac);
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rval = readl(&mmchost->reg->idie) &
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~(SUNXI_MMC_IDIE_TXIRQ|SUNXI_MMC_IDIE_RXIRQ);
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if (data->flags & MMC_DATA_WRITE)
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rval |= SUNXI_MMC_IDIE_TXIRQ;
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else
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rval |= SUNXI_MMC_IDIE_RXIRQ;
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writel(rval, &mmchost->reg->idie);
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writel((u32) pdes, &mmchost->reg->dlba);
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writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3),
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&mmchost->reg->ftrglevel);
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return 0;
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}
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static void mmc_enable_dma_accesses(struct mmc *mmc, int dma)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned int gctrl = readl(&mmchost->reg->gctrl);
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if (dma)
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gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB;
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else
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gctrl |= SUNXI_MMC_GCTRL_ACCESS_BY_AHB;
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writel(gctrl, &mmchost->reg->gctrl);
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}
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static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
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unsigned int done_bit, const char *what)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned int status;
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do {
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status = readl(&mmchost->reg->rint);
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if (!timeout_msecs-- ||
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(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
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debug("%s timeout %x\n", what,
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status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
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return TIMEOUT;
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}
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udelay(1000);
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} while (!(status & done_bit));
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return 0;
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}
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static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct sunxi_mmc_host *mmchost = mmc->priv;
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unsigned int cmdval = SUNXI_MMC_CMD_START;
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unsigned int timeout_msecs;
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int error = 0;
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unsigned int status = 0;
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unsigned int usedma = 0;
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unsigned int bytecnt = 0;
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if (mmchost->fatal_err)
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return -1;
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if (cmd->resp_type & MMC_RSP_BUSY)
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debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
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if (cmd->cmdidx == 12)
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return 0;
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if (!cmd->cmdidx)
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cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
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if (cmd->resp_type & MMC_RSP_PRESENT)
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cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
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if (cmd->resp_type & MMC_RSP_136)
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cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
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if (cmd->resp_type & MMC_RSP_CRC)
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cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
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if (data) {
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if ((u32) data->dest & 0x3) {
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error = -1;
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goto out;
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}
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cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
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if (data->flags & MMC_DATA_WRITE)
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cmdval |= SUNXI_MMC_CMD_WRITE;
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if (data->blocks > 1)
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cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
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writel(data->blocksize, &mmchost->reg->blksz);
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writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
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}
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debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
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cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
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writel(cmd->cmdarg, &mmchost->reg->arg);
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if (!data)
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writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
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/*
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* transfer data and check status
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* STATREG[2] : FIFO empty
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* STATREG[3] : FIFO full
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*/
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if (data) {
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int ret = 0;
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bytecnt = data->blocksize * data->blocks;
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debug("trans data %d bytes\n", bytecnt);
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#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD)
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if (bytecnt > 64) {
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#else
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if (0) {
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#endif
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usedma = 1;
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mmc_enable_dma_accesses(mmc, 1);
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ret = mmc_trans_data_by_dma(mmc, data);
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writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
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} else {
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mmc_enable_dma_accesses(mmc, 0);
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writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
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ret = mmc_trans_data_by_cpu(mmc, data);
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}
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if (ret) {
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error = readl(&mmchost->reg->rint) & \
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||
|
SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
|
||
|
error = TIMEOUT;
|
||
|
goto out;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
|
||
|
if (error)
|
||
|
goto out;
|
||
|
|
||
|
if (data) {
|
||
|
timeout_msecs = usedma ? 120 * bytecnt : 120;
|
||
|
debug("cacl timeout %x msec\n", timeout_msecs);
|
||
|
error = mmc_rint_wait(mmc, timeout_msecs,
|
||
|
data->blocks > 1 ?
|
||
|
SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
|
||
|
SUNXI_MMC_RINT_DATA_OVER,
|
||
|
"data");
|
||
|
if (error)
|
||
|
goto out;
|
||
|
}
|
||
|
|
||
|
if (cmd->resp_type & MMC_RSP_BUSY) {
|
||
|
timeout_msecs = 2000;
|
||
|
do {
|
||
|
status = readl(&mmchost->reg->status);
|
||
|
if (!timeout_msecs--) {
|
||
|
debug("busy timeout\n");
|
||
|
error = TIMEOUT;
|
||
|
goto out;
|
||
|
}
|
||
|
udelay(1000);
|
||
|
} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
|
||
|
}
|
||
|
|
||
|
if (cmd->resp_type & MMC_RSP_136) {
|
||
|
cmd->response[0] = readl(&mmchost->reg->resp3);
|
||
|
cmd->response[1] = readl(&mmchost->reg->resp2);
|
||
|
cmd->response[2] = readl(&mmchost->reg->resp1);
|
||
|
cmd->response[3] = readl(&mmchost->reg->resp0);
|
||
|
debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
||
|
cmd->response[3], cmd->response[2],
|
||
|
cmd->response[1], cmd->response[0]);
|
||
|
} else {
|
||
|
cmd->response[0] = readl(&mmchost->reg->resp0);
|
||
|
debug("mmc resp 0x%08x\n", cmd->response[0]);
|
||
|
}
|
||
|
out:
|
||
|
if (data && usedma) {
|
||
|
/* IDMASTAREG
|
||
|
* IDST[0] : idma tx int
|
||
|
* IDST[1] : idma rx int
|
||
|
* IDST[2] : idma fatal bus error
|
||
|
* IDST[4] : idma descriptor invalid
|
||
|
* IDST[5] : idma error summary
|
||
|
* IDST[8] : idma normal interrupt sumary
|
||
|
* IDST[9] : idma abnormal interrupt sumary
|
||
|
*/
|
||
|
status = readl(&mmchost->reg->idst);
|
||
|
writel(status, &mmchost->reg->idst);
|
||
|
writel(0, &mmchost->reg->idie);
|
||
|
writel(0, &mmchost->reg->dmac);
|
||
|
writel(readl(&mmchost->reg->gctrl) & ~SUNXI_MMC_GCTRL_DMA_ENABLE,
|
||
|
&mmchost->reg->gctrl);
|
||
|
}
|
||
|
if (error < 0) {
|
||
|
writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
|
||
|
mmc_update_clk(mmc);
|
||
|
}
|
||
|
writel(0xffffffff, &mmchost->reg->rint);
|
||
|
writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
|
||
|
&mmchost->reg->gctrl);
|
||
|
|
||
|
return error;
|
||
|
}
|
||
|
|
||
|
static const struct mmc_ops sunxi_mmc_ops = {
|
||
|
.send_cmd = mmc_send_cmd,
|
||
|
.set_ios = mmc_set_ios,
|
||
|
.init = mmc_core_init,
|
||
|
};
|
||
|
|
||
|
int sunxi_mmc_init(int sdc_no)
|
||
|
{
|
||
|
struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
|
||
|
|
||
|
memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
|
||
|
|
||
|
cfg->name = "SUNXI SD/MMC";
|
||
|
cfg->ops = &sunxi_mmc_ops;
|
||
|
|
||
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
||
|
cfg->host_caps = MMC_MODE_4BIT;
|
||
|
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
||
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
||
|
|
||
|
cfg->f_min = 400000;
|
||
|
cfg->f_max = 52000000;
|
||
|
|
||
|
mmc_resource_init(sdc_no);
|
||
|
mmc_clk_io_on(sdc_no);
|
||
|
|
||
|
if (mmc_create(cfg, &mmc_host[sdc_no]) == NULL)
|
||
|
return -1;
|
||
|
|
||
|
return 0;
|
||
|
}
|