2014-11-13 14:42:23 +09:00
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/*
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* From Coreboot
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*
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2011 Google Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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2016-01-18 08:11:15 +09:00
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#include <dm.h>
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2014-11-13 14:42:23 +09:00
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/sandybridge.h>
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2016-01-18 08:11:17 +09:00
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static void sandybridge_setup_lpc_bars(pci_dev_t lpc_dev)
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2014-11-13 14:42:23 +09:00
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{
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/* Setting up Southbridge. In the northbridge code. */
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debug("Setting up static southbridge registers\n");
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2015-03-06 04:25:15 +09:00
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x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
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2014-11-13 14:42:23 +09:00
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2015-03-06 04:25:15 +09:00
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x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
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x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
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2014-11-13 14:42:23 +09:00
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debug("Disabling watchdog reboot\n");
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setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
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outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
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2016-01-18 08:11:17 +09:00
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}
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2014-11-13 14:42:23 +09:00
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2016-01-18 08:11:17 +09:00
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static void sandybridge_setup_northbridge_bars(struct udevice *dev)
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{
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2014-11-13 14:42:23 +09:00
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/* Set up all hardcoded northbridge BARs */
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debug("Setting up static registers\n");
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2016-01-18 08:11:17 +09:00
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dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
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dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
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dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1);
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dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
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2014-11-13 14:42:23 +09:00
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/* 64MB - busses 0-63 */
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2016-01-18 08:11:17 +09:00
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dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
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dm_pci_write_config32(dev, PCIEXBAR + 4,
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(0LL + DEFAULT_PCIEXBAR) >> 32);
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dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1);
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dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
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2014-11-13 14:42:23 +09:00
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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2016-01-18 08:11:17 +09:00
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dm_pci_write_config8(dev, PAM0, 0x30);
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dm_pci_write_config8(dev, PAM1, 0x33);
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dm_pci_write_config8(dev, PAM2, 0x33);
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dm_pci_write_config8(dev, PAM3, 0x33);
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dm_pci_write_config8(dev, PAM4, 0x33);
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dm_pci_write_config8(dev, PAM5, 0x33);
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dm_pci_write_config8(dev, PAM6, 0x33);
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2014-11-13 14:42:23 +09:00
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}
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static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
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{
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u32 reg32;
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u16 reg16;
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u8 reg8;
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2015-03-06 04:25:15 +09:00
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reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID);
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2014-11-13 14:42:23 +09:00
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switch (reg16) {
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case 0x0102: /* GT1 Desktop */
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case 0x0106: /* GT1 Mobile */
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case 0x010a: /* GT1 Server */
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case 0x0112: /* GT2 Desktop */
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case 0x0116: /* GT2 Mobile */
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case 0x0122: /* GT2 Desktop >=1.3GHz */
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case 0x0126: /* GT2 Mobile >=1.3GHz */
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case 0x0156: /* IvyBridge */
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case 0x0166: /* IvyBridge */
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break;
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default:
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debug("Graphics not supported by this CPU/chipset\n");
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return;
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}
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debug("Initialising Graphics\n");
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/* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
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2015-03-06 04:25:15 +09:00
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reg16 = x86_pci_read_config16(pch_dev, GGC);
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2014-11-13 14:42:23 +09:00
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reg16 &= ~0x00f8;
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reg16 |= 1 << 3;
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/* Program GTT memory by setting GGC[9:8] = 2MB */
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reg16 &= ~0x0300;
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reg16 |= 2 << 8;
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/* Enable VGA decode */
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reg16 &= ~0x0002;
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2015-03-06 04:25:15 +09:00
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x86_pci_write_config16(pch_dev, GGC, reg16);
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2014-11-13 14:42:23 +09:00
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/* Enable 256MB aperture */
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2015-03-06 04:25:15 +09:00
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reg8 = x86_pci_read_config8(video_dev, MSAC);
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2014-11-13 14:42:23 +09:00
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reg8 &= ~0x06;
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reg8 |= 0x02;
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2015-03-06 04:25:15 +09:00
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x86_pci_write_config8(video_dev, MSAC, reg8);
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2014-11-13 14:42:23 +09:00
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/* Erratum workarounds */
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reg32 = readl(MCHBAR_REG(0x5f00));
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reg32 |= (1 << 9) | (1 << 10);
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writel(reg32, MCHBAR_REG(0x5f00));
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/* Enable SA Clock Gating */
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reg32 = readl(MCHBAR_REG(0x5f00));
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writel(reg32 | 1, MCHBAR_REG(0x5f00));
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/* GPU RC6 workaround for sighting 366252 */
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reg32 = readl(MCHBAR_REG(0x5d14));
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reg32 |= (1 << 31);
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writel(reg32, MCHBAR_REG(0x5d14));
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/* VLW */
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reg32 = readl(MCHBAR_REG(0x6120));
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reg32 &= ~(1 << 0);
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writel(reg32, MCHBAR_REG(0x6120));
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reg32 = readl(MCHBAR_REG(0x5418));
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reg32 |= (1 << 4) | (1 << 5);
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writel(reg32, MCHBAR_REG(0x5418));
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}
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void sandybridge_early_init(int chipset_type)
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{
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pci_dev_t pch_dev = PCH_DEV;
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pci_dev_t video_dev = PCH_VIDEO_DEV;
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/* Device Enable */
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2015-03-06 04:25:15 +09:00
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x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
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2014-11-13 14:42:23 +09:00
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sandybridge_setup_graphics(pch_dev, video_dev);
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}
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2016-01-18 08:11:15 +09:00
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static int bd82x6x_northbridge_probe(struct udevice *dev)
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{
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2016-01-18 08:11:16 +09:00
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const int chipset_type = SANDYBRIDGE_MOBILE;
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u32 capid0_a;
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u8 reg8;
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if (gd->flags & GD_FLG_RELOC)
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return 0;
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/* Device ID Override Enable should be done very early */
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dm_pci_read_config32(dev, 0xe4, &capid0_a);
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if (capid0_a & (1 << 10)) {
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dm_pci_read_config8(dev, 0xf3, ®8);
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reg8 &= ~7; /* Clear 2:0 */
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if (chipset_type == SANDYBRIDGE_MOBILE)
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reg8 |= 1; /* Set bit 0 */
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dm_pci_write_config8(dev, 0xf3, reg8);
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}
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2016-01-18 08:11:17 +09:00
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sandybridge_setup_lpc_bars(PCH_LPC_DEV);
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sandybridge_setup_northbridge_bars(dev);
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2016-01-18 08:11:15 +09:00
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return 0;
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}
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static const struct udevice_id bd82x6x_northbridge_ids[] = {
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{ .compatible = "intel,bd82x6x-northbridge" },
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{ }
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};
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U_BOOT_DRIVER(bd82x6x_northbridge_drv) = {
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.name = "bd82x6x_northbridge",
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.id = UCLASS_NORTHBRIDGE,
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.of_match = bd82x6x_northbridge_ids,
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.probe = bd82x6x_northbridge_probe,
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};
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