mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 08:58:52 +09:00
401 lines
10 KiB
C
401 lines
10 KiB
C
![]() |
/*
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* Partially derived from board code for digsyMTC,
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* (C) Copyright 2009
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* Grzegorz Bernacki, Semihalf, gjb@semihalf.com
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*
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* (C) Copyright 2012
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* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <net.h>
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#include <pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define SDRAM_MODE 0x00CD0000
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#define SDRAM_CONTROL 0x504F0000
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#define SDRAM_CONFIG1 0xD2322800
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#define SDRAM_CONFIG2 0x8AD70000
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enum ifm_sensor_type {
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O2DNT = 0x00, /* !< O2DNT 32MB */
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O2DNT2 = 0x01, /* !< O2DNT2 64MB */
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O3DNT = 0x02, /* !< O3DNT 32MB */
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O3DNT_MIN = 0x40, /* !< O3DNT Minerva 32MB */
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UNKNOWN = 0xff, /* !< Unknow sensor */
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};
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static enum ifm_sensor_type gt_ifm_sensor_type;
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#ifndef CONFIG_SYS_RAMBOOT
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static void sdram_start(int hi_addr)
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{
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struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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long control = SDRAM_CONTROL | hi_addr_bit;
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/* unlock mode register */
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out_be32(&sdram->ctrl, control | 0x80000000);
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/* precharge all banks */
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out_be32(&sdram->ctrl, control | 0x80000002);
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/* auto refresh */
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out_be32(&sdram->ctrl, control | 0x80000004);
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/* set mode register */
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out_be32(&sdram->mode, SDRAM_MODE);
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/* normal operation */
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out_be32(&sdram->ctrl, control);
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
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* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
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*/
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phys_size_t initdram(int board_type)
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{
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struct mpc5xxx_mmap_ctl *mmap_ctl =
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(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
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struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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uint svr, pvr;
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if (gt_ifm_sensor_type == O2DNT2) {
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/* activate SDRAM CS1 */
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setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000);
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}
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#ifndef CONFIG_SYS_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */
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out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */
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/* setup config registers */
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out_be32(&sdram->config1, SDRAM_CONFIG1);
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out_be32(&sdram->config2, SDRAM_CONFIG2);
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20))
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dramsize = 0;
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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out_be32(&mmap_ctl->sdram0,
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(0x13 + __builtin_ffs(dramsize >> 20) - 1));
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} else {
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out_be32(&mmap_ctl->sdram0, 0); /* disabled */
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}
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/* let SDRAM CS1 start right after CS0 */
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out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */
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/* find RAM size using SDRAM CS1 only */
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if (!dramsize)
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sdram_start(0);
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test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
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0x80000000);
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if (!dramsize) {
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sdram_start(1);
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test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
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0x80000000);
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}
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if (test1 > test2) {
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sdram_start(0);
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dramsize2 = test1;
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} else {
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dramsize2 = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize2 < (1 << 20))
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dramsize2 = 0;
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/* set SDRAM CS1 size according to the amount of RAM found */
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if (dramsize2 > 0) {
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out_be32(&mmap_ctl->sdram1, (dramsize |
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(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
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} else {
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out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */
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}
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#else /* CONFIG_SYS_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF;
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if (dramsize >= 0x13)
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dramsize = (1 << (dramsize - 0x13)) << 20;
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else
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dramsize = 0;
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF;
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if (dramsize2 >= 0x13)
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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else
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dramsize2 = 0;
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#endif /* CONFIG_SYS_RAMBOOT */
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/*
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* On MPC5200B we need to set the special configuration delay in the
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* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
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* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
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*
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* "The SDelay should be written to a value of 0x00000004. It is
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* required to account for changes caused by normal wafer processing
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* parameters."
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*/
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svr = get_svr();
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pvr = get_pvr();
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if ((SVR_MJREV(svr) >= 2) &&
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(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
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out_be32(&sdram->sdelay, 0x04);
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return dramsize + dramsize2;
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}
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#define GPT_GPIO_IN 0x4
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int checkboard(void)
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{
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struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
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unsigned char board_config = 0;
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int i;
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/* switch gpt0 - gpt7 to input */
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for (i = 0; i < 7; i++)
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out_be32(&gpt[i].emsr, GPT_GPIO_IN);
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/* get configuration byte on timer-port */
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for (i = 0; i < 7; i++)
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board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i);
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puts("Board: ");
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switch (board_config) {
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case 0:
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puts("O2DNT\n");
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gt_ifm_sensor_type = O2DNT;
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break;
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case 1:
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puts("O3DNT\n");
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gt_ifm_sensor_type = O3DNT;
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break;
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case 2:
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puts("O2DNT2\n");
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gt_ifm_sensor_type = O2DNT2;
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break;
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case 64:
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puts("O3DNT Minerva\n");
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gt_ifm_sensor_type = O3DNT_MIN;
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break;
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default:
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puts("Unknown\n");
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gt_ifm_sensor_type = UNKNOWN;
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break;
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}
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return 0;
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}
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int board_early_init_r(void)
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{
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struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
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/*
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* Now, when we are in RAM, enable flash write access for detection
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* process. Note that CS_BOOT cannot be cleared when executing in flash.
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*/
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clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */
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/* disable CS_BOOT */
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clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
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/* enable CS0 */
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setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
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return 0;
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}
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#define MIIM_LXT971_LED_CFG_REG 0x14
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#define LXT971_LED_CFG_LINK_STATUS 0x4000
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#define LXT971_LED_CFG_RX_TX_ACTIVITY 0x0700
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#define LXT971_LED_CFG_LINK_ACTIVITY 0x00D0
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#define LXT971_LED_CFG_PULSE_STRETCH 0x0002
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/*
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* Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
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*/
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void reset_phy(void)
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{
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/*
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* Set LED configuration bits.
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* It can't be done in misc_init_r() since FEC is not
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* initialized at this time. Therefore we do it here.
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*/
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miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG,
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LXT971_LED_CFG_LINK_STATUS |
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LXT971_LED_CFG_RX_TX_ACTIVITY |
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LXT971_LED_CFG_LINK_ACTIVITY |
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LXT971_LED_CFG_PULSE_STRETCH);
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}
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#if defined(CONFIG_POST)
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/*
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* Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
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* is left open, no keypress is detected.
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*/
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int post_hotkeys_pressed(void)
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{
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
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/*
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* Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
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* CODEC or UART mode. Consumer IrDA should still be possible.
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*/
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clrbits_be32(&gpio->port_config, 0x07000000);
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setbits_be32(&gpio->port_config, 0x03000000);
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/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
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setbits_be32(&gpio->simple_gpioe, 0x20000000);
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/* Configure GPIO_IRDA_1 as input */
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clrbits_be32(&gpio->simple_ddr, 0x20000000);
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return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1;
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}
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#endif
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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void pci_init_board(void)
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{
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pci_mpc5xxx_init(&hose);
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}
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#endif
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
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static void ft_adapt_flash_base(void *blob)
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{
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flash_info_t *dev = &flash_info[0];
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int off;
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struct fdt_property *prop;
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int len;
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u32 *reg, *reg2;
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off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
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if (off < 0) {
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printf("Could not find fsl,mpc5200b-lpb node.\n");
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return;
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}
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/* found compatible property */
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prop = fdt_get_property_w(blob, off, "ranges", &len);
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if (prop) {
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reg = reg2 = (u32 *)&prop->data[0];
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reg[2] = dev->start[0];
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reg[3] = dev->size;
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fdt_setprop(blob, off, "ranges", reg2, len);
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} else
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printf("Could not find ranges\n");
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}
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extern ulong flash_get_size(phys_addr_t base, int banknum);
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/* Update the flash baseaddr settings */
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int update_flash_size(int flash_size)
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{
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struct mpc5xxx_mmap_ctl *mm =
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(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
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flash_info_t *dev;
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int i;
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int size = 0;
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unsigned long base = 0x0;
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u32 *cs_reg = (u32 *)&mm->cs0_start;
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for (i = 0; i < 2; i++) {
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dev = &flash_info[i];
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if (dev->size) {
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/* calculate new base addr for this chipselect */
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base -= dev->size;
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out_be32(cs_reg, START_REG(base));
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cs_reg++;
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out_be32(cs_reg, STOP_REG(base, dev->size));
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cs_reg++;
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/* recalculate the sectoraddr in the cfi driver */
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size += flash_get_size(base, i);
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}
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}
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flash_protect_default();
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gd->bd->bi_flashstart = base;
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return 0;
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}
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#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
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void ft_board_setup(void *blob, bd_t *bd)
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{
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int phy_addr = CONFIG_PHY_ADDR;
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char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
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ft_cpu_setup(blob, bd);
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#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
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#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
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/* Update reg property in all nor flash nodes too */
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fdt_fixup_nor_flash_size(blob);
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#endif
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ft_adapt_flash_base(blob);
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#endif
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/* fix up the phy address */
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do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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