2015-04-21 20:38:20 +09:00
|
|
|
if ARCH_SOCFPGA
|
|
|
|
|
2016-09-13 14:18:41 +09:00
|
|
|
config SPL_LIBCOMMON_SUPPORT
|
|
|
|
default y
|
|
|
|
|
2016-09-13 14:18:42 +09:00
|
|
|
config SPL_LIBDISK_SUPPORT
|
|
|
|
default y
|
|
|
|
|
2016-09-13 14:18:43 +09:00
|
|
|
config SPL_LIBGENERIC_SUPPORT
|
|
|
|
default y
|
|
|
|
|
2016-09-13 14:18:44 +09:00
|
|
|
config SPL_MMC_SUPPORT
|
|
|
|
default y if DM_MMC
|
|
|
|
|
2016-09-13 14:18:48 +09:00
|
|
|
config SPL_NAND_SUPPORT
|
|
|
|
default y if SPL_NAND_DENALI
|
|
|
|
|
2016-09-13 14:18:56 +09:00
|
|
|
config SPL_SERIAL_SUPPORT
|
|
|
|
default y
|
|
|
|
|
2016-09-13 14:18:57 +09:00
|
|
|
config SPL_SPI_FLASH_SUPPORT
|
2016-09-13 14:18:58 +09:00
|
|
|
default y if SPL_SPI_SUPPORT
|
|
|
|
|
|
|
|
config SPL_SPI_SUPPORT
|
2016-09-13 14:18:57 +09:00
|
|
|
default y if DM_SPI
|
|
|
|
|
2016-09-13 14:19:02 +09:00
|
|
|
config SPL_WATCHDOG_SUPPORT
|
|
|
|
default y
|
|
|
|
|
2015-08-03 04:57:57 +09:00
|
|
|
config TARGET_SOCFPGA_ARRIA5
|
|
|
|
bool
|
2015-12-03 04:31:25 +09:00
|
|
|
select TARGET_SOCFPGA_GEN5
|
2015-08-03 04:57:57 +09:00
|
|
|
|
|
|
|
config TARGET_SOCFPGA_CYCLONE5
|
|
|
|
bool
|
2015-12-03 04:31:25 +09:00
|
|
|
select TARGET_SOCFPGA_GEN5
|
|
|
|
|
|
|
|
config TARGET_SOCFPGA_GEN5
|
|
|
|
bool
|
2015-08-03 04:57:57 +09:00
|
|
|
|
2015-04-21 20:38:20 +09:00
|
|
|
choice
|
|
|
|
prompt "Altera SOCFPGA board select"
|
2015-05-13 04:46:23 +09:00
|
|
|
optional
|
2015-04-21 20:38:20 +09:00
|
|
|
|
2015-08-03 04:57:57 +09:00
|
|
|
config TARGET_SOCFPGA_ARRIA5_SOCDK
|
|
|
|
bool "Altera SOCFPGA SoCDK (Arria V)"
|
|
|
|
select TARGET_SOCFPGA_ARRIA5
|
2015-04-21 20:38:20 +09:00
|
|
|
|
2015-08-03 04:57:57 +09:00
|
|
|
config TARGET_SOCFPGA_CYCLONE5_SOCDK
|
|
|
|
bool "Altera SOCFPGA SoCDK (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
2015-04-21 20:38:20 +09:00
|
|
|
|
2015-08-03 08:37:28 +09:00
|
|
|
config TARGET_SOCFPGA_DENX_MCVEVK
|
|
|
|
bool "DENX MCVEVK (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2015-11-24 01:06:27 +09:00
|
|
|
config TARGET_SOCFPGA_EBV_SOCRATES
|
|
|
|
bool "EBV SoCrates (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2016-06-07 19:37:23 +09:00
|
|
|
config TARGET_SOCFPGA_IS1
|
|
|
|
bool "IS1 (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2015-12-02 02:09:52 +09:00
|
|
|
config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
|
|
|
|
bool "samtec VIN|ING FPGA (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2016-06-08 09:57:05 +09:00
|
|
|
config TARGET_SOCFPGA_SR1500
|
|
|
|
bool "SR1500 (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2015-09-02 07:41:52 +09:00
|
|
|
config TARGET_SOCFPGA_TERASIC_DE0_NANO
|
|
|
|
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2015-06-22 00:28:53 +09:00
|
|
|
config TARGET_SOCFPGA_TERASIC_SOCKIT
|
|
|
|
bool "Terasic SoCkit (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2015-04-21 20:38:20 +09:00
|
|
|
endchoice
|
|
|
|
|
|
|
|
config SYS_BOARD
|
2015-08-11 04:24:53 +09:00
|
|
|
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
|
|
|
|
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
|
2015-09-02 07:41:52 +09:00
|
|
|
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
|
2016-06-07 19:37:23 +09:00
|
|
|
default "is1" if TARGET_SOCFPGA_IS1
|
2015-08-03 08:37:28 +09:00
|
|
|
default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
|
2015-06-22 00:28:53 +09:00
|
|
|
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
|
2015-11-24 01:06:27 +09:00
|
|
|
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
|
2015-11-18 19:06:09 +09:00
|
|
|
default "sr1500" if TARGET_SOCFPGA_SR1500
|
2015-12-02 02:09:52 +09:00
|
|
|
default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
|
2015-04-21 20:38:20 +09:00
|
|
|
|
|
|
|
config SYS_VENDOR
|
2015-08-03 04:57:57 +09:00
|
|
|
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
|
|
|
|
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
|
2015-08-03 08:37:28 +09:00
|
|
|
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
|
2015-11-24 01:06:27 +09:00
|
|
|
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
|
2015-12-02 02:09:52 +09:00
|
|
|
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
|
2015-09-02 07:41:52 +09:00
|
|
|
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
|
2015-06-22 00:28:53 +09:00
|
|
|
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
|
2015-04-21 20:38:20 +09:00
|
|
|
|
|
|
|
config SYS_SOC
|
|
|
|
default "socfpga"
|
|
|
|
|
|
|
|
config SYS_CONFIG_NAME
|
2015-09-23 07:01:32 +09:00
|
|
|
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
|
|
|
|
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
|
2015-09-02 07:41:52 +09:00
|
|
|
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
|
2016-06-07 19:37:23 +09:00
|
|
|
default "socfpga_is1" if TARGET_SOCFPGA_IS1
|
2015-08-03 08:37:28 +09:00
|
|
|
default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
|
2015-06-22 00:28:53 +09:00
|
|
|
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
|
2015-11-24 01:06:27 +09:00
|
|
|
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
|
2015-11-18 19:06:09 +09:00
|
|
|
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
|
2015-12-02 02:09:52 +09:00
|
|
|
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
|
2015-04-21 20:38:20 +09:00
|
|
|
|
|
|
|
endif
|