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https://github.com/brain-hackers/u-boot-brain
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176 lines
3.6 KiB
C
176 lines
3.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell Armada 37xx SoC Watchdog Driver
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*
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* Marek Behun <marek.behun@nic.cz>
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*/
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#include <common.h>
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#include <dm.h>
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#include <wdt.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct a37xx_wdt {
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void __iomem *sel_reg;
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void __iomem *reg;
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ulong clk_rate;
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u64 timeout;
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};
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/*
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* We use Counter 1 for watchdog timer, because so does Marvell's Linux by
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* default.
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*/
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#define CNTR_CTRL 0x10
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#define CNTR_CTRL_ENABLE 0x0001
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#define CNTR_CTRL_ACTIVE 0x0002
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#define CNTR_CTRL_MODE_MASK 0x000c
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#define CNTR_CTRL_MODE_ONESHOT 0x0000
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#define CNTR_CTRL_PRESCALE_MASK 0xff00
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#define CNTR_CTRL_PRESCALE_MIN 2
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#define CNTR_CTRL_PRESCALE_SHIFT 8
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#define CNTR_COUNT_LOW 0x14
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#define CNTR_COUNT_HIGH 0x18
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static void set_counter_value(struct a37xx_wdt *priv)
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{
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writel(priv->timeout & 0xffffffff, priv->reg + CNTR_COUNT_LOW);
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writel(priv->timeout >> 32, priv->reg + CNTR_COUNT_HIGH);
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}
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static void a37xx_wdt_enable(struct a37xx_wdt *priv)
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{
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u32 reg = readl(priv->reg + CNTR_CTRL);
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reg |= CNTR_CTRL_ENABLE;
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writel(reg, priv->reg + CNTR_CTRL);
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}
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static void a37xx_wdt_disable(struct a37xx_wdt *priv)
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{
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u32 reg = readl(priv->reg + CNTR_CTRL);
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reg &= ~CNTR_CTRL_ENABLE;
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writel(reg, priv->reg + CNTR_CTRL);
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}
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static int a37xx_wdt_reset(struct udevice *dev)
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{
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struct a37xx_wdt *priv = dev_get_priv(dev);
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if (!priv->timeout)
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return -EINVAL;
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a37xx_wdt_disable(priv);
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set_counter_value(priv);
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a37xx_wdt_enable(priv);
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return 0;
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}
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static int a37xx_wdt_expire_now(struct udevice *dev, ulong flags)
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{
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struct a37xx_wdt *priv = dev_get_priv(dev);
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a37xx_wdt_disable(priv);
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priv->timeout = 0;
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set_counter_value(priv);
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a37xx_wdt_enable(priv);
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return 0;
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}
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static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags)
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{
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struct a37xx_wdt *priv = dev_get_priv(dev);
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u32 reg;
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reg = readl(priv->reg + CNTR_CTRL);
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if (reg & CNTR_CTRL_ACTIVE)
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return -EBUSY;
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/* set mode */
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reg = (reg & ~CNTR_CTRL_MODE_MASK) | CNTR_CTRL_MODE_ONESHOT;
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/* set prescaler to the min value */
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reg &= ~CNTR_CTRL_PRESCALE_MASK;
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reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
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priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN;
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writel(reg, priv->reg + CNTR_CTRL);
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set_counter_value(priv);
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a37xx_wdt_enable(priv);
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return 0;
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}
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static int a37xx_wdt_stop(struct udevice *dev)
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{
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struct a37xx_wdt *priv = dev_get_priv(dev);
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a37xx_wdt_disable(priv);
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return 0;
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}
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static int a37xx_wdt_probe(struct udevice *dev)
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{
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struct a37xx_wdt *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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addr = dev_read_addr_index(dev, 0);
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if (addr == FDT_ADDR_T_NONE)
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goto err;
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priv->sel_reg = (void __iomem *)addr;
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addr = dev_read_addr_index(dev, 1);
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if (addr == FDT_ADDR_T_NONE)
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goto err;
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priv->reg = (void __iomem *)addr;
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priv->clk_rate = (ulong)get_ref_clk() * 1000000;
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a37xx_wdt_disable(priv);
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/*
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* We use timer 1 as watchdog timer (because Marvell's Linux uses that
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* timer as default), therefore we only set bit TIMER1_IS_WCHDOG_TIMER.
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*/
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writel(1 << 1, priv->sel_reg);
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return 0;
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err:
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dev_err(dev, "no io address\n");
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return -ENODEV;
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}
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static const struct wdt_ops a37xx_wdt_ops = {
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.start = a37xx_wdt_start,
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.reset = a37xx_wdt_reset,
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.stop = a37xx_wdt_stop,
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.expire_now = a37xx_wdt_expire_now,
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};
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static const struct udevice_id a37xx_wdt_ids[] = {
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{ .compatible = "marvell,armada-3700-wdt" },
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{}
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};
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U_BOOT_DRIVER(a37xx_wdt) = {
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.name = "armada_37xx_wdt",
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.id = UCLASS_WDT,
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.of_match = a37xx_wdt_ids,
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.probe = a37xx_wdt_probe,
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.priv_auto_alloc_size = sizeof(struct a37xx_wdt),
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.ops = &a37xx_wdt_ops,
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};
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