2012-10-07 20:36:06 +09:00
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/*
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* Copyright (C) 2012 Lucas Stach
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*
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2013-07-08 16:37:19 +09:00
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* SPDX-License-Identifier: GPL-2.0+
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2012-10-07 20:36:06 +09:00
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch-tegra/board.h>
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2015-03-26 09:31:53 +09:00
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#include <asm/gpio.h>
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2012-10-07 20:36:06 +09:00
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#ifdef CONFIG_TEGRA_MMC
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2013-02-21 21:31:30 +09:00
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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void pin_mux_mmc(void)
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2012-10-07 20:36:06 +09:00
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{
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funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
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2014-03-22 03:28:58 +09:00
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pinmux_tristate_disable(PMUX_PINGRP_GMB);
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2012-10-07 20:36:06 +09:00
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}
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#endif
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2015-03-26 09:31:53 +09:00
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#ifdef CONFIG_TEGRA_NAND
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void pin_mux_nand(void)
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{
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funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
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}
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#endif
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#ifdef CONFIG_USB_EHCI_TEGRA
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void pin_mux_usb(void)
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{
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/* module internal USB bus to connect ethernet chipset */
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funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
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/* ULPI reference clock output */
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pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
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pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
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/* PHY reset GPIO */
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pinmux_tristate_disable(PMUX_PINGRP_UAC);
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/* VBus GPIO */
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pinmux_tristate_disable(PMUX_PINGRP_DTE);
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/* USB 1 aka Tegra USB port 3 VBus */
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pinmux_tristate_disable(PMUX_PINGRP_SPIG);
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}
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#endif
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