2007-07-26 09:25:33 +09:00
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_QE 1 /* Has QE */
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2009-05-23 07:23:25 +09:00
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#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
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2007-07-26 09:25:33 +09:00
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/*
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* System Clock Setup
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*/
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#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
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#endif
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/*
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* Hardware Reset Configuration Word
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_HRCW_LOW (\
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2007-07-26 09:25:33 +09:00
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_2X1 |\
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HRCWL_VCO_1X2 |\
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HRCWL_CSB_TO_CLKIN_2X1 |\
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HRCWL_CORE_TO_CSB_2_5X1 |\
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HRCWL_CE_PLL_VCO_DIV_2 |\
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HRCWL_CE_PLL_DIV_1X1 |\
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HRCWL_CE_TO_PLL_1X3)
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_HRCW_HIGH (\
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2007-07-26 09:25:33 +09:00
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HRCWH_PCI_HOST |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_BIG_ENDIAN |\
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HRCWH_LALE_NORMAL)
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/*
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* System IO Config
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_SICRL 0x00000000
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2007-07-26 09:25:33 +09:00
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/*
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* IMMR new address
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_IMMR 0xE0000000
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2007-07-26 09:25:33 +09:00
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2008-03-21 02:15:34 +09:00
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/*
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* System performance
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
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#define CONFIG_SYS_SPCR_OPT 1
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2008-03-21 02:15:34 +09:00
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2007-07-26 09:25:33 +09:00
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/*
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* DDR Setup
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*/
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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2007-07-26 09:25:33 +09:00
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#undef CONFIG_SPD_EEPROM
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#if defined(CONFIG_SPD_EEPROM)
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/* Determine DDR configuration from I2C interface
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*/
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
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#else
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/* Manually set up DDR parameters
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*/
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_DDR_SIZE 64 /* MB */
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_9)
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2008-03-21 02:15:34 +09:00
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/* 0x80010101 */
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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2008-03-21 02:15:28 +09:00
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/* 0x00220802 */
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
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| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
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| (5 << TIMING_CFG1_CASLAT_SHIFT) \
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| (3 << TIMING_CFG1_REFREC_SHIFT) \
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| (2 << TIMING_CFG1_WRREC_SHIFT) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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2008-03-21 02:15:34 +09:00
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/* 0x26253222 */
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (31 << TIMING_CFG2_CPO_SHIFT) \
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| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
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2008-03-21 02:15:34 +09:00
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/* 0x1f9048c7 */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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2008-03-21 02:15:28 +09:00
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/* 0x02000000 */
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
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| (0x0232 << SDRAM_MODE_SD_SHIFT))
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2008-03-21 02:15:34 +09:00
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/* 0x44480232 */
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_DDR_MODE2 0x8000c000
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#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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2008-03-21 02:15:28 +09:00
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/* 0x03200064 */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
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2008-03-21 02:15:28 +09:00
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| SDRAM_CFG_SDRAM_TYPE_DDR2 \
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2011-10-12 13:57:12 +09:00
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| SDRAM_CFG_32_BE)
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2008-03-21 02:15:28 +09:00
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/* 0x43080000 */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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2007-07-26 09:25:33 +09:00
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#endif
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/*
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* Memory test
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*/
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2008-10-16 22:01:15 +09:00
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x03f00000
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2007-07-26 09:25:33 +09:00
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/*
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* The reserved memory
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*/
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2010-10-08 04:51:12 +09:00
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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2007-07-26 09:25:33 +09:00
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2008-10-16 22:01:15 +09:00
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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2007-07-26 09:25:33 +09:00
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#else
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2008-10-16 22:01:15 +09:00
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#undef CONFIG_SYS_RAMBOOT
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2007-07-26 09:25:33 +09:00
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#endif
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2008-10-16 22:01:15 +09:00
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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2016-07-08 12:25:14 +09:00
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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2012-07-01 08:29:20 +09:00
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
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2007-07-26 09:25:33 +09:00
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/*
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* Initial RAM Base Address Setup
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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2007-07-26 09:25:33 +09:00
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/*
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* Local Bus Configuration & Clock Setup
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*/
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2009-09-26 08:19:44 +09:00
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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2007-07-26 09:25:33 +09:00
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/*
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* FLASH on the Local Bus
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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2008-08-13 08:40:42 +09:00
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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2007-07-26 09:25:33 +09:00
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2011-10-12 13:57:12 +09:00
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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2011-10-12 13:57:30 +09:00
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
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2007-07-26 09:25:33 +09:00
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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2011-10-12 13:57:30 +09:00
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| BR_PS_16 /* 16 bit port */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
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| OR_GPCM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX_SET \
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| OR_GPCM_EHTR_SET \
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| OR_GPCM_EAD)
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/* 0xFE006FF7 */
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2007-07-26 09:25:33 +09:00
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2011-10-12 13:57:12 +09:00
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
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2007-07-26 09:25:33 +09:00
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2008-10-16 22:01:15 +09:00
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#undef CONFIG_SYS_FLASH_CHECKSUM
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2007-07-26 09:25:33 +09:00
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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2007-07-26 09:25:33 +09:00
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_BAUDRATE_TABLE \
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2011-10-12 13:57:12 +09:00
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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2007-07-26 09:25:33 +09:00
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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2007-07-26 09:25:33 +09:00
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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2010-04-16 07:36:05 +09:00
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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2007-07-26 09:25:33 +09:00
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/* I2C */
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2012-10-24 20:48:22 +09:00
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
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2007-07-26 09:25:33 +09:00
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/*
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2008-03-21 02:15:39 +09:00
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* Config on-board EEPROM
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2007-07-26 09:25:33 +09:00
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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2007-07-26 09:25:33 +09:00
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
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#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
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#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
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2007-07-26 09:25:33 +09:00
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#ifdef CONFIG_PCI
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2013-05-30 16:06:12 +09:00
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#define CONFIG_PCI_INDIRECT_BRIDGE
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2008-03-29 04:15:38 +09:00
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#define CONFIG_PCI_SKIP_HOST_BRIDGE
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2007-07-26 09:25:33 +09:00
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#undef CONFIG_EEPRO100
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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2007-07-26 09:25:33 +09:00
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#endif /* CONFIG_PCI */
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/*
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* QE UEC ethernet configuration
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*/
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#define CONFIG_UEC_ETH
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2010-07-27 08:34:57 +09:00
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#define CONFIG_ETHPRIME "UEC0"
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2007-07-26 09:25:33 +09:00
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#define CONFIG_UEC_ETH1 /* ETH3 */
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#ifdef CONFIG_UEC_ETH1
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2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
|
|
|
|
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
|
|
|
|
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
|
|
|
|
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
|
|
|
|
#define CONFIG_SYS_UEC1_PHY_ADDR 4
|
2011-04-13 14:37:12 +09:00
|
|
|
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
|
2010-01-20 17:04:28 +09:00
|
|
|
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
|
2007-07-26 09:25:33 +09:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#define CONFIG_UEC_ETH2 /* ETH4 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_UEC_ETH2
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
|
|
|
|
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
|
|
|
|
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
|
|
|
|
#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
|
|
|
|
#define CONFIG_SYS_UEC2_PHY_ADDR 0
|
2011-04-13 14:37:12 +09:00
|
|
|
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
|
2010-01-20 17:04:28 +09:00
|
|
|
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
|
2007-07-26 09:25:33 +09:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Environment
|
|
|
|
*/
|
2008-10-16 22:01:15 +09:00
|
|
|
#ifndef CONFIG_SYS_RAMBOOT
|
2011-10-12 13:57:12 +09:00
|
|
|
#define CONFIG_ENV_ADDR \
|
|
|
|
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
2008-09-11 05:48:06 +09:00
|
|
|
#define CONFIG_ENV_SECT_SIZE 0x20000
|
|
|
|
#define CONFIG_ENV_SIZE 0x2000
|
2007-07-26 09:25:33 +09:00
|
|
|
#else
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
2008-09-11 05:48:06 +09:00
|
|
|
#define CONFIG_ENV_SIZE 0x2000
|
2007-07-26 09:25:33 +09:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* BOOTP options
|
|
|
|
*/
|
|
|
|
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
|
|
#define CONFIG_BOOTP_BOOTPATH
|
|
|
|
#define CONFIG_BOOTP_GATEWAY
|
|
|
|
#define CONFIG_BOOTP_HOSTNAME
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Command line configuration.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Miscellaneous configurable options
|
|
|
|
*/
|
2011-10-12 13:57:12 +09:00
|
|
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
|
|
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* For booting Linux, the board info and command line data
|
2010-09-11 07:42:32 +09:00
|
|
|
* have to be in the first 256 MB of memory, since this is
|
2007-07-26 09:25:33 +09:00
|
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
|
|
*/
|
2011-10-12 13:57:12 +09:00
|
|
|
/* Initial Memory map for Linux */
|
|
|
|
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
|
2016-07-08 12:25:15 +09:00
|
|
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Core HID Setup
|
|
|
|
*/
|
mpc83xx: turn on icache in core initialization to improve u-boot boot time
before, MPC8349ITX boots u-boot in 4.3sec:
column1 is elapsed time since first message
column2 is elapsed time since previous message
column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA: Configured for compact flash
0.032 0.000: I2C: ready
0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI: Bus Dev VenId DevId Class Int
2.652 0.011: 00 10 1095 3114 0180 00
2.652 0.000: PCI: Bus Dev VenId DevId Class Int
2.652 0.000: In: serial
2.652 0.000: Out: serial
2.652 0.000: Err: serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE: Bus 0: .** Timeout **
after, MPC8349ITX boots u-boot in 3.0sec:
0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA: Configured for compact flash
0.038 0.000: I2C: ready
0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI: Bus Dev VenId DevId Class Int
1.390 0.000: 00 10 1095 3114 0180 00
1.390 0.000: PCI: Bus Dev VenId DevId Class Int
1.400 0.010: In: serial
1.400 0.000: Out: serial
1.400 0.000: Err: serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE: Bus 0: .** Timeout **
also tested on these boards (albeit with a less accurate
boottime measurement method):
seconds: before after
8349MDS ~2.6 ~2.2
8360MDS ~2.8 ~2.6
8313RDB ~2.5 ~2.3 #nand boot
837xRDB ~3.1 ~2.3
also tested on an 8323ERDB.
v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-21 09:37:54 +09:00
|
|
|
#define CONFIG_SYS_HID0_INIT 0x000000000
|
|
|
|
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
|
|
|
|
HID0_ENABLE_INSTRUCTION_CACHE)
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_HID2 HID2_HBE
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* MMU Setup
|
|
|
|
*/
|
2008-05-09 09:02:12 +09:00
|
|
|
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
/* DDR: cache cacheable */
|
2011-10-12 13:57:12 +09:00
|
|
|
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
|
2011-10-12 13:57:28 +09:00
|
|
|
| BATL_PP_RW \
|
2011-10-12 13:57:12 +09:00
|
|
|
| BATL_MEMCOHERENCE)
|
|
|
|
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
|
|
|
|
| BATU_BL_256M \
|
|
|
|
| BATU_VS \
|
|
|
|
| BATU_VP)
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
|
|
|
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
|
2011-10-12 13:57:12 +09:00
|
|
|
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
|
2011-10-12 13:57:28 +09:00
|
|
|
| BATL_PP_RW \
|
2011-10-12 13:57:12 +09:00
|
|
|
| BATL_CACHEINHIBIT \
|
|
|
|
| BATL_GUARDEDSTORAGE)
|
|
|
|
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
|
|
|
|
| BATU_BL_4M \
|
|
|
|
| BATU_VS \
|
|
|
|
| BATU_VP)
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
|
|
|
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
2011-10-12 13:57:12 +09:00
|
|
|
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
|
2011-10-12 13:57:28 +09:00
|
|
|
| BATL_PP_RW \
|
2011-10-12 13:57:12 +09:00
|
|
|
| BATL_MEMCOHERENCE)
|
|
|
|
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
|
|
|
|
| BATU_BL_32M \
|
|
|
|
| BATU_VS \
|
|
|
|
| BATU_VP)
|
|
|
|
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
|
2011-10-12 13:57:28 +09:00
|
|
|
| BATL_PP_RW \
|
2011-10-12 13:57:12 +09:00
|
|
|
| BATL_CACHEINHIBIT \
|
|
|
|
| BATL_GUARDEDSTORAGE)
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
2007-07-26 09:25:33 +09:00
|
|
|
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_IBAT3L (0)
|
|
|
|
#define CONFIG_SYS_IBAT3U (0)
|
|
|
|
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
|
|
|
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
/* Stack in dcache: cacheable, no memory coherence */
|
2011-10-12 13:57:28 +09:00
|
|
|
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
|
2011-10-12 13:57:12 +09:00
|
|
|
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
|
|
|
|
| BATU_BL_128K \
|
|
|
|
| BATU_VS \
|
|
|
|
| BATU_VP)
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
|
|
|
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
/* PCI MEM space: cacheable */
|
2011-10-12 13:57:12 +09:00
|
|
|
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
|
2011-10-12 13:57:28 +09:00
|
|
|
| BATL_PP_RW \
|
2011-10-12 13:57:12 +09:00
|
|
|
| BATL_MEMCOHERENCE)
|
|
|
|
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
|
|
|
|
| BATU_BL_256M \
|
|
|
|
| BATU_VS \
|
|
|
|
| BATU_VP)
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
|
|
|
|
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
2007-07-26 09:25:33 +09:00
|
|
|
/* PCI MMIO space: cache-inhibit and guarded */
|
2011-10-12 13:57:12 +09:00
|
|
|
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
|
2011-10-12 13:57:28 +09:00
|
|
|
| BATL_PP_RW \
|
2011-10-12 13:57:12 +09:00
|
|
|
| BATL_CACHEINHIBIT \
|
|
|
|
| BATL_GUARDEDSTORAGE)
|
|
|
|
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
|
|
|
|
| BATU_BL_256M \
|
|
|
|
| BATU_VS \
|
|
|
|
| BATU_VP)
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
|
|
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
2007-07-26 09:25:33 +09:00
|
|
|
#else
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_IBAT5L (0)
|
|
|
|
#define CONFIG_SYS_IBAT5U (0)
|
|
|
|
#define CONFIG_SYS_IBAT6L (0)
|
|
|
|
#define CONFIG_SYS_IBAT6U (0)
|
|
|
|
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
|
|
|
|
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
|
|
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
|
|
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
2007-07-26 09:25:33 +09:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Nothing in BAT7 */
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_IBAT7L (0)
|
|
|
|
#define CONFIG_SYS_IBAT7U (0)
|
|
|
|
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
|
|
|
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
#if (CONFIG_CMD_KGDB)
|
|
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Environment Configuration
|
|
|
|
*/
|
|
|
|
#define CONFIG_ENV_OVERWRITE
|
|
|
|
|
2011-10-12 13:57:12 +09:00
|
|
|
#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
|
|
|
|
#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
|
2007-07-26 09:25:33 +09:00
|
|
|
|
2011-10-12 13:57:12 +09:00
|
|
|
/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
|
|
|
|
* (see CONFIG_SYS_I2C_EEPROM) */
|
|
|
|
/* MAC address offset in I2C EEPROM */
|
|
|
|
#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
|
2008-03-28 03:34:43 +09:00
|
|
|
|
2011-10-12 13:57:12 +09:00
|
|
|
#define CONFIG_NETDEV "eth1"
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
#define CONFIG_HOSTNAME mpc8323erdb
|
2011-10-13 22:03:47 +09:00
|
|
|
#define CONFIG_ROOTPATH "/nfsroot"
|
2011-10-13 22:03:48 +09:00
|
|
|
#define CONFIG_BOOTFILE "uImage"
|
2011-10-12 13:57:12 +09:00
|
|
|
/* U-Boot image on TFTP server */
|
|
|
|
#define CONFIG_UBOOTPATH "u-boot.bin"
|
|
|
|
#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
|
|
|
|
#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
|
2007-07-26 09:25:33 +09:00
|
|
|
|
2011-10-12 13:57:12 +09:00
|
|
|
/* default location for tftp and bootm */
|
|
|
|
#define CONFIG_LOADADDR 800000
|
2007-07-26 09:25:33 +09:00
|
|
|
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
2011-10-12 13:57:12 +09:00
|
|
|
"netdev=" CONFIG_NETDEV "\0" \
|
|
|
|
"uboot=" CONFIG_UBOOTPATH "\0" \
|
2007-07-26 09:25:33 +09:00
|
|
|
"tftpflash=tftp $loadaddr $uboot;" \
|
2012-09-24 00:41:24 +09:00
|
|
|
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" +$filesize; " \
|
|
|
|
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" +$filesize; " \
|
|
|
|
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" $filesize; " \
|
|
|
|
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" +$filesize; " \
|
|
|
|
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" $filesize\0" \
|
2009-08-22 06:34:38 +09:00
|
|
|
"fdtaddr=780000\0" \
|
2011-10-12 13:57:12 +09:00
|
|
|
"fdtfile=" CONFIG_FDTFILE "\0" \
|
2007-07-26 09:25:33 +09:00
|
|
|
"ramdiskaddr=1000000\0" \
|
2011-10-12 13:57:12 +09:00
|
|
|
"ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
|
2007-07-26 09:25:33 +09:00
|
|
|
"console=ttyS0\0" \
|
|
|
|
"setbootargs=setenv bootargs " \
|
2011-10-12 13:57:12 +09:00
|
|
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
|
2007-07-26 09:25:33 +09:00
|
|
|
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
2011-10-12 13:57:12 +09:00
|
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
|
|
|
|
"$netdev:off "\
|
2007-07-26 09:25:33 +09:00
|
|
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
|
|
|
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
|
|
"setenv rootdev /dev/nfs;" \
|
|
|
|
"run setbootargs;" \
|
|
|
|
"run setipargs;" \
|
|
|
|
"tftp $loadaddr $bootfile;" \
|
|
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
|
|
"bootm $loadaddr - $fdtaddr"
|
|
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv rootdev /dev/ram;" \
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"run setbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#endif /* __CONFIG_H */
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