2007-08-17 09:23:50 +09:00
|
|
|
/*
|
|
|
|
*
|
|
|
|
* (C) Copyright 2000-2003
|
|
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
|
|
*
|
2012-03-27 06:49:06 +09:00
|
|
|
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
|
2007-08-17 09:23:50 +09:00
|
|
|
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
|
|
|
*
|
2013-07-08 16:37:19 +09:00
|
|
|
* SPDX-License-Identifier: GPL-2.0+
|
2007-08-17 09:23:50 +09:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
|
|
|
#include <asm/processor.h>
|
|
|
|
|
|
|
|
#include <asm/immap.h>
|
2012-03-27 06:49:06 +09:00
|
|
|
#include <asm/io.h>
|
2007-08-17 09:23:50 +09:00
|
|
|
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
/*
|
|
|
|
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
|
|
|
|
*/
|
|
|
|
int get_clocks(void)
|
|
|
|
{
|
2012-03-27 06:49:06 +09:00
|
|
|
pll_t *pll = (pll_t *)(MMAP_PLL);
|
2007-08-17 09:23:50 +09:00
|
|
|
|
2012-03-27 06:49:06 +09:00
|
|
|
out_be32(&pll->syncr, PLL_SYNCR_MFD(1));
|
2007-08-17 09:23:50 +09:00
|
|
|
|
2012-03-27 06:49:06 +09:00
|
|
|
while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
|
|
|
|
;
|
2007-08-18 21:33:02 +09:00
|
|
|
|
2008-10-16 22:01:15 +09:00
|
|
|
gd->bus_clk = CONFIG_SYS_CLK;
|
2007-08-17 09:23:50 +09:00
|
|
|
gd->cpu_clk = (gd->bus_clk * 2);
|
2007-08-18 21:33:02 +09:00
|
|
|
|
2008-08-19 06:01:19 +09:00
|
|
|
#ifdef CONFIG_FSL_I2C
|
2012-12-14 05:48:49 +09:00
|
|
|
gd->arch.i2c1_clk = gd->bus_clk;
|
2008-08-19 06:01:19 +09:00
|
|
|
#endif
|
|
|
|
|
2007-08-17 09:23:50 +09:00
|
|
|
return (0);
|
|
|
|
}
|