u-boot-brain/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h

/*
 *  Copyright (C) 2012 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _SOCFPGA_BASE_ADDRS_H_
#define _SOCFPGA_BASE_ADDRS_H_

#define SOCFPGA_L3REGS_ADDRESS 0xff800000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000

#endif /* _SOCFPGA_BASE_ADDRS_H_ */
ARM: Add Altera SOCFPGA Cyclone5 Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2 2012-10-04 15:46:02 +09:00			`/*`
			`* Copyright (C) 2012 Altera Corporation <www.altera.com>`
			`*`
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> 2013-07-08 16:37:19 +09:00			`* SPDX-License-Identifier: GPL-2.0+`
ARM: Add Altera SOCFPGA Cyclone5 Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2 2012-10-04 15:46:02 +09:00			`*/`

			`#ifndef _SOCFPGA_BASE_ADDRS_H_`
			`#define _SOCFPGA_BASE_ADDRS_H_`

			`#define SOCFPGA_L3REGS_ADDRESS 0xff800000`
			`#define SOCFPGA_UART0_ADDRESS 0xffc02000`
			`#define SOCFPGA_UART1_ADDRESS 0xffc03000`
			`#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000`
			`#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000`

			`#endif /* _SOCFPGA_BASE_ADDRS_H_ */`