mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
1394 lines
46 KiB
C
1394 lines
46 KiB
C
![]() |
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __MESON_REGISTERS_H
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#define __MESON_REGISTERS_H
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/* Shift all registers by 2 */
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#define _REG(reg) ((reg) << 2)
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#define writel_bits(mask, val, addr) \
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writel((readl(addr) & ~(mask)) | (val), addr)
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/* vpp2 */
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#define VPP2_DUMMY_DATA 0x1900
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#define VPP2_LINE_IN_LENGTH 0x1901
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#define VPP2_PIC_IN_HEIGHT 0x1902
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#define VPP2_SCALE_COEF_IDX 0x1903
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#define VPP2_SCALE_COEF 0x1904
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#define VPP2_VSC_REGION12_STARTP 0x1905
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#define VPP2_VSC_REGION34_STARTP 0x1906
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#define VPP2_VSC_REGION4_ENDP 0x1907
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#define VPP2_VSC_START_PHASE_STEP 0x1908
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#define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
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#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a
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#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b
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#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c
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#define VPP2_VSC_PHASE_CTRL 0x190d
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#define VPP2_VSC_INI_PHASE 0x190e
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#define VPP2_HSC_REGION12_STARTP 0x1910
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#define VPP2_HSC_REGION34_STARTP 0x1911
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#define VPP2_HSC_REGION4_ENDP 0x1912
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#define VPP2_HSC_START_PHASE_STEP 0x1913
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#define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914
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#define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915
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#define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916
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#define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917
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#define VPP2_HSC_PHASE_CTRL 0x1918
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#define VPP2_SC_MISC 0x1919
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#define VPP2_PREBLEND_VD1_H_START_END 0x191a
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#define VPP2_PREBLEND_VD1_V_START_END 0x191b
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#define VPP2_POSTBLEND_VD1_H_START_END 0x191c
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#define VPP2_POSTBLEND_VD1_V_START_END 0x191d
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#define VPP2_PREBLEND_H_SIZE 0x1920
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#define VPP2_POSTBLEND_H_SIZE 0x1921
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#define VPP2_HOLD_LINES 0x1922
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#define VPP2_BLEND_ONECOLOR_CTRL 0x1923
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#define VPP2_PREBLEND_CURRENT_XY 0x1924
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#define VPP2_POSTBLEND_CURRENT_XY 0x1925
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#define VPP2_MISC 0x1926
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#define VPP2_OFIFO_SIZE 0x1927
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#define VPP2_FIFO_STATUS 0x1928
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#define VPP2_SMOKE_CTRL 0x1929
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#define VPP2_SMOKE1_VAL 0x192a
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#define VPP2_SMOKE2_VAL 0x192b
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#define VPP2_SMOKE1_H_START_END 0x192d
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#define VPP2_SMOKE1_V_START_END 0x192e
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#define VPP2_SMOKE2_H_START_END 0x192f
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#define VPP2_SMOKE2_V_START_END 0x1930
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#define VPP2_SCO_FIFO_CTRL 0x1933
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#define VPP2_HSC_PHASE_CTRL1 0x1934
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#define VPP2_HSC_INI_PAT_CTRL 0x1935
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#define VPP2_VADJ_CTRL 0x1940
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#define VPP2_VADJ1_Y 0x1941
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#define VPP2_VADJ1_MA_MB 0x1942
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#define VPP2_VADJ1_MC_MD 0x1943
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#define VPP2_VADJ2_Y 0x1944
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#define VPP2_VADJ2_MA_MB 0x1945
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#define VPP2_VADJ2_MC_MD 0x1946
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#define VPP2_MATRIX_PROBE_COLOR 0x195c
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#define VPP2_MATRIX_HL_COLOR 0x195d
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#define VPP2_MATRIX_PROBE_POS 0x195e
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#define VPP2_MATRIX_CTRL 0x195f
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#define VPP2_MATRIX_COEF00_01 0x1960
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#define VPP2_MATRIX_COEF02_10 0x1961
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#define VPP2_MATRIX_COEF11_12 0x1962
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#define VPP2_MATRIX_COEF20_21 0x1963
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#define VPP2_MATRIX_COEF22 0x1964
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#define VPP2_MATRIX_OFFSET0_1 0x1965
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#define VPP2_MATRIX_OFFSET2 0x1966
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#define VPP2_MATRIX_PRE_OFFSET0_1 0x1967
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#define VPP2_MATRIX_PRE_OFFSET2 0x1968
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#define VPP2_DUMMY_DATA1 0x1969
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#define VPP2_GAINOFF_CTRL0 0x196a
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#define VPP2_GAINOFF_CTRL1 0x196b
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#define VPP2_GAINOFF_CTRL2 0x196c
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#define VPP2_GAINOFF_CTRL3 0x196d
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#define VPP2_GAINOFF_CTRL4 0x196e
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#define VPP2_CHROMA_ADDR_PORT 0x1970
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#define VPP2_CHROMA_DATA_PORT 0x1971
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#define VPP2_GCLK_CTRL0 0x1972
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#define VPP2_GCLK_CTRL1 0x1973
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#define VPP2_SC_GCLK_CTRL 0x1974
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#define VPP2_MISC1 0x1976
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#define VPP2_DNLP_CTRL_00 0x1981
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#define VPP2_DNLP_CTRL_01 0x1982
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#define VPP2_DNLP_CTRL_02 0x1983
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#define VPP2_DNLP_CTRL_03 0x1984
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#define VPP2_DNLP_CTRL_04 0x1985
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#define VPP2_DNLP_CTRL_05 0x1986
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#define VPP2_DNLP_CTRL_06 0x1987
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#define VPP2_DNLP_CTRL_07 0x1988
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#define VPP2_DNLP_CTRL_08 0x1989
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#define VPP2_DNLP_CTRL_09 0x198a
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#define VPP2_DNLP_CTRL_10 0x198b
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#define VPP2_DNLP_CTRL_11 0x198c
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#define VPP2_DNLP_CTRL_12 0x198d
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#define VPP2_DNLP_CTRL_13 0x198e
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#define VPP2_DNLP_CTRL_14 0x198f
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#define VPP2_DNLP_CTRL_15 0x1990
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#define VPP2_VE_ENABLE_CTRL 0x19a1
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#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2
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#define VPP2_VE_DEMO_CENTER_BAR 0x19a3
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#define VPP2_VE_H_V_SIZE 0x19a4
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#define VPP2_VDO_MEAS_CTRL 0x19a8
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#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9
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#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa
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#define VPP2_OSD_VSC_PHASE_STEP 0x19c0
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#define VPP2_OSD_VSC_INI_PHASE 0x19c1
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#define VPP2_OSD_VSC_CTRL0 0x19c2
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#define VPP2_OSD_HSC_PHASE_STEP 0x19c3
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#define VPP2_OSD_HSC_INI_PHASE 0x19c4
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#define VPP2_OSD_HSC_CTRL0 0x19c5
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#define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6
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#define VPP2_OSD_SC_DUMMY_DATA 0x19c7
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#define VPP2_OSD_SC_CTRL0 0x19c8
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#define VPP2_OSD_SCI_WH_M1 0x19c9
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#define VPP2_OSD_SCO_H_START_END 0x19ca
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#define VPP2_OSD_SCO_V_START_END 0x19cb
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#define VPP2_OSD_SCALE_COEF_IDX 0x19cc
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#define VPP2_OSD_SCALE_COEF 0x19cd
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#define VPP2_INT_LINE_NUM 0x19ce
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/* viu */
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#define VIU_ADDR_START 0x1a00
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#define VIU_ADDR_END 0x1aff
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#define VIU_SW_RESET 0x1a01
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#define VIU_MISC_CTRL0 0x1a06
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#define VIU_MISC_CTRL1 0x1a07
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#define D2D3_INTF_LENGTH 0x1a08
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#define D2D3_INTF_CTRL0 0x1a09
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#define VIU_OSD1_CTRL_STAT 0x1a10
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#define VIU_OSD1_CTRL_STAT2 0x1a2d
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#define VIU_OSD1_COLOR_ADDR 0x1a11
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#define VIU_OSD1_COLOR 0x1a12
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#define VIU_OSD1_TCOLOR_AG0 0x1a17
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#define VIU_OSD1_TCOLOR_AG1 0x1a18
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#define VIU_OSD1_TCOLOR_AG2 0x1a19
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#define VIU_OSD1_TCOLOR_AG3 0x1a1a
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#define VIU_OSD1_BLK0_CFG_W0 0x1a1b
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#define VIU_OSD1_BLK1_CFG_W0 0x1a1f
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#define VIU_OSD1_BLK2_CFG_W0 0x1a23
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#define VIU_OSD1_BLK3_CFG_W0 0x1a27
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#define VIU_OSD1_BLK0_CFG_W1 0x1a1c
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#define VIU_OSD1_BLK1_CFG_W1 0x1a20
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#define VIU_OSD1_BLK2_CFG_W1 0x1a24
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#define VIU_OSD1_BLK3_CFG_W1 0x1a28
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#define VIU_OSD1_BLK0_CFG_W2 0x1a1d
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#define VIU_OSD1_BLK1_CFG_W2 0x1a21
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#define VIU_OSD1_BLK2_CFG_W2 0x1a25
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#define VIU_OSD1_BLK3_CFG_W2 0x1a29
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#define VIU_OSD1_BLK0_CFG_W3 0x1a1e
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#define VIU_OSD1_BLK1_CFG_W3 0x1a22
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#define VIU_OSD1_BLK2_CFG_W3 0x1a26
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#define VIU_OSD1_BLK3_CFG_W3 0x1a2a
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#define VIU_OSD1_BLK0_CFG_W4 0x1a13
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#define VIU_OSD1_BLK1_CFG_W4 0x1a14
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#define VIU_OSD1_BLK2_CFG_W4 0x1a15
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#define VIU_OSD1_BLK3_CFG_W4 0x1a16
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#define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b
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#define VIU_OSD1_TEST_RDDATA 0x1a2c
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#define VIU_OSD1_PROT_CTRL 0x1a2e
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#define VIU_OSD2_CTRL_STAT 0x1a30
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#define VIU_OSD2_CTRL_STAT2 0x1a4d
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#define VIU_OSD2_COLOR_ADDR 0x1a31
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#define VIU_OSD2_COLOR 0x1a32
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#define VIU_OSD2_HL1_H_START_END 0x1a33
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#define VIU_OSD2_HL1_V_START_END 0x1a34
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#define VIU_OSD2_HL2_H_START_END 0x1a35
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#define VIU_OSD2_HL2_V_START_END 0x1a36
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#define VIU_OSD2_TCOLOR_AG0 0x1a37
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#define VIU_OSD2_TCOLOR_AG1 0x1a38
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#define VIU_OSD2_TCOLOR_AG2 0x1a39
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#define VIU_OSD2_TCOLOR_AG3 0x1a3a
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#define VIU_OSD2_BLK0_CFG_W0 0x1a3b
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#define VIU_OSD2_BLK1_CFG_W0 0x1a3f
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#define VIU_OSD2_BLK2_CFG_W0 0x1a43
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#define VIU_OSD2_BLK3_CFG_W0 0x1a47
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#define VIU_OSD2_BLK0_CFG_W1 0x1a3c
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#define VIU_OSD2_BLK1_CFG_W1 0x1a40
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#define VIU_OSD2_BLK2_CFG_W1 0x1a44
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#define VIU_OSD2_BLK3_CFG_W1 0x1a48
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#define VIU_OSD2_BLK0_CFG_W2 0x1a3d
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#define VIU_OSD2_BLK1_CFG_W2 0x1a41
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#define VIU_OSD2_BLK2_CFG_W2 0x1a45
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#define VIU_OSD2_BLK3_CFG_W2 0x1a49
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#define VIU_OSD2_BLK0_CFG_W3 0x1a3e
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#define VIU_OSD2_BLK1_CFG_W3 0x1a42
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#define VIU_OSD2_BLK2_CFG_W3 0x1a46
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#define VIU_OSD2_BLK3_CFG_W3 0x1a4a
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#define VIU_OSD2_BLK0_CFG_W4 0x1a64
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#define VIU_OSD2_BLK1_CFG_W4 0x1a65
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#define VIU_OSD2_BLK2_CFG_W4 0x1a66
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#define VIU_OSD2_BLK3_CFG_W4 0x1a67
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#define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b
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#define VIU_OSD2_TEST_RDDATA 0x1a4c
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#define VIU_OSD2_PROT_CTRL 0x1a4e
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#define VD1_IF0_GEN_REG 0x1a50
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#define VD1_IF0_CANVAS0 0x1a51
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#define VD1_IF0_CANVAS1 0x1a52
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#define VD1_IF0_LUMA_X0 0x1a53
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#define VD1_IF0_LUMA_Y0 0x1a54
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#define VD1_IF0_CHROMA_X0 0x1a55
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#define VD1_IF0_CHROMA_Y0 0x1a56
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#define VD1_IF0_LUMA_X1 0x1a57
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#define VD1_IF0_LUMA_Y1 0x1a58
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#define VD1_IF0_CHROMA_X1 0x1a59
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#define VD1_IF0_CHROMA_Y1 0x1a5a
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#define VD1_IF0_RPT_LOOP 0x1a5b
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#define VD1_IF0_LUMA0_RPT_PAT 0x1a5c
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#define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d
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#define VD1_IF0_LUMA1_RPT_PAT 0x1a5e
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#define VD1_IF0_CHROMA1_RPT_PAT 0x1a5f
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#define VD1_IF0_LUMA_PSEL 0x1a60
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#define VD1_IF0_CHROMA_PSEL 0x1a61
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#define VD1_IF0_DUMMY_PIXEL 0x1a62
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#define VD1_IF0_LUMA_FIFO_SIZE 0x1a63
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#define VD1_IF0_RANGE_MAP_Y 0x1a6a
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#define VD1_IF0_RANGE_MAP_CB 0x1a6b
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#define VD1_IF0_RANGE_MAP_CR 0x1a6c
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#define VD1_IF0_GEN_REG2 0x1a6d
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#define VD1_IF0_PROT_CNTL 0x1a6e
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#define VIU_VD1_FMT_CTRL 0x1a68
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#define VIU_VD1_FMT_W 0x1a69
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#define VD2_IF0_GEN_REG 0x1a70
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#define VD2_IF0_CANVAS0 0x1a71
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#define VD2_IF0_CANVAS1 0x1a72
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#define VD2_IF0_LUMA_X0 0x1a73
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#define VD2_IF0_LUMA_Y0 0x1a74
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#define VD2_IF0_CHROMA_X0 0x1a75
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#define VD2_IF0_CHROMA_Y0 0x1a76
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#define VD2_IF0_LUMA_X1 0x1a77
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#define VD2_IF0_LUMA_Y1 0x1a78
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#define VD2_IF0_CHROMA_X1 0x1a79
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#define VD2_IF0_CHROMA_Y1 0x1a7a
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#define VD2_IF0_RPT_LOOP 0x1a7b
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#define VD2_IF0_LUMA0_RPT_PAT 0x1a7c
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#define VD2_IF0_CHROMA0_RPT_PAT 0x1a7d
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#define VD2_IF0_LUMA1_RPT_PAT 0x1a7e
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#define VD2_IF0_CHROMA1_RPT_PAT 0x1a7f
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#define VD2_IF0_LUMA_PSEL 0x1a80
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#define VD2_IF0_CHROMA_PSEL 0x1a81
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#define VD2_IF0_DUMMY_PIXEL 0x1a82
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#define VD2_IF0_LUMA_FIFO_SIZE 0x1a83
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#define VD2_IF0_RANGE_MAP_Y 0x1a8a
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#define VD2_IF0_RANGE_MAP_CB 0x1a8b
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#define VD2_IF0_RANGE_MAP_CR 0x1a8c
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#define VD2_IF0_GEN_REG2 0x1a8d
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#define VD2_IF0_PROT_CNTL 0x1a8e
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#define VIU_VD2_FMT_CTRL 0x1a88
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#define VIU_VD2_FMT_W 0x1a89
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/* VIU Matrix Registers */
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#define VIU_OSD1_MATRIX_CTRL 0x1a90
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#define VIU_OSD1_MATRIX_COEF00_01 0x1a91
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#define VIU_OSD1_MATRIX_COEF02_10 0x1a92
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#define VIU_OSD1_MATRIX_COEF11_12 0x1a93
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#define VIU_OSD1_MATRIX_COEF20_21 0x1a94
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#define VIU_OSD1_MATRIX_COLMOD_COEF42 0x1a95
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#define VIU_OSD1_MATRIX_OFFSET0_1 0x1a96
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#define VIU_OSD1_MATRIX_OFFSET2 0x1a97
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#define VIU_OSD1_MATRIX_PRE_OFFSET0_1 0x1a98
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#define VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a99
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#define VIU_OSD1_MATRIX_COEF22_30 0x1a9d
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#define VIU_OSD1_MATRIX_COEF31_32 0x1a9e
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#define VIU_OSD1_MATRIX_COEF40_41 0x1a9f
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||
|
#define VD1_IF0_GEN_REG3 0x1aa7
|
||
|
#define VIU_OSD1_EOTF_CTL 0x1ad4
|
||
|
#define VIU_OSD1_EOTF_COEF00_01 0x1ad5
|
||
|
#define VIU_OSD1_EOTF_COEF02_10 0x1ad6
|
||
|
#define VIU_OSD1_EOTF_COEF11_12 0x1ad7
|
||
|
#define VIU_OSD1_EOTF_COEF20_21 0x1ad8
|
||
|
#define VIU_OSD1_EOTF_COEF22_RS 0x1ad9
|
||
|
#define VIU_OSD1_EOTF_LUT_ADDR_PORT 0x1ada
|
||
|
#define VIU_OSD1_EOTF_LUT_DATA_PORT 0x1adb
|
||
|
#define VIU_OSD1_OETF_CTL 0x1adc
|
||
|
#define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add
|
||
|
#define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade
|
||
|
#define AFBC_ENABLE 0x1ae0
|
||
|
|
||
|
/* vpp */
|
||
|
#define VPP_DUMMY_DATA 0x1d00
|
||
|
#define VPP_LINE_IN_LENGTH 0x1d01
|
||
|
#define VPP_PIC_IN_HEIGHT 0x1d02
|
||
|
#define VPP_SCALE_COEF_IDX 0x1d03
|
||
|
#define VPP_SCALE_COEF 0x1d04
|
||
|
#define VPP_VSC_REGION12_STARTP 0x1d05
|
||
|
#define VPP_VSC_REGION34_STARTP 0x1d06
|
||
|
#define VPP_VSC_REGION4_ENDP 0x1d07
|
||
|
#define VPP_VSC_START_PHASE_STEP 0x1d08
|
||
|
#define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09
|
||
|
#define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a
|
||
|
#define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b
|
||
|
#define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c
|
||
|
#define VPP_VSC_PHASE_CTRL 0x1d0d
|
||
|
#define VPP_VSC_INI_PHASE 0x1d0e
|
||
|
#define VPP_HSC_REGION12_STARTP 0x1d10
|
||
|
#define VPP_HSC_REGION34_STARTP 0x1d11
|
||
|
#define VPP_HSC_REGION4_ENDP 0x1d12
|
||
|
#define VPP_HSC_START_PHASE_STEP 0x1d13
|
||
|
#define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14
|
||
|
#define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15
|
||
|
#define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16
|
||
|
#define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17
|
||
|
#define VPP_HSC_PHASE_CTRL 0x1d18
|
||
|
#define VPP_SC_MISC 0x1d19
|
||
|
#define VPP_PREBLEND_VD1_H_START_END 0x1d1a
|
||
|
#define VPP_PREBLEND_VD1_V_START_END 0x1d1b
|
||
|
#define VPP_POSTBLEND_VD1_H_START_END 0x1d1c
|
||
|
#define VPP_POSTBLEND_VD1_V_START_END 0x1d1d
|
||
|
#define VPP_BLEND_VD2_H_START_END 0x1d1e
|
||
|
#define VPP_BLEND_VD2_V_START_END 0x1d1f
|
||
|
#define VPP_PREBLEND_H_SIZE 0x1d20
|
||
|
#define VPP_POSTBLEND_H_SIZE 0x1d21
|
||
|
#define VPP_HOLD_LINES 0x1d22
|
||
|
#define VPP_BLEND_ONECOLOR_CTRL 0x1d23
|
||
|
#define VPP_PREBLEND_CURRENT_XY 0x1d24
|
||
|
#define VPP_POSTBLEND_CURRENT_XY 0x1d25
|
||
|
#define VPP_MISC 0x1d26
|
||
|
#define VPP_PREBLEND_ENABLE BIT(6)
|
||
|
#define VPP_POSTBLEND_ENABLE BIT(7)
|
||
|
#define VPP_OSD2_ALPHA_PREMULT BIT(8)
|
||
|
#define VPP_OSD1_ALPHA_PREMULT BIT(9)
|
||
|
#define VPP_VD1_POSTBLEND BIT(10)
|
||
|
#define VPP_VD2_POSTBLEND BIT(11)
|
||
|
#define VPP_OSD1_POSTBLEND BIT(12)
|
||
|
#define VPP_OSD2_POSTBLEND BIT(13)
|
||
|
#define VPP_VD1_PREBLEND BIT(14)
|
||
|
#define VPP_VD2_PREBLEND BIT(15)
|
||
|
#define VPP_OSD1_PREBLEND BIT(16)
|
||
|
#define VPP_OSD2_PREBLEND BIT(17)
|
||
|
#define VPP_COLOR_MNG_ENABLE BIT(28)
|
||
|
#define VPP_OFIFO_SIZE 0x1d27
|
||
|
#define VPP_FIFO_STATUS 0x1d28
|
||
|
#define VPP_SMOKE_CTRL 0x1d29
|
||
|
#define VPP_SMOKE1_VAL 0x1d2a
|
||
|
#define VPP_SMOKE2_VAL 0x1d2b
|
||
|
#define VPP_SMOKE3_VAL 0x1d2c
|
||
|
#define VPP_SMOKE1_H_START_END 0x1d2d
|
||
|
#define VPP_SMOKE1_V_START_END 0x1d2e
|
||
|
#define VPP_SMOKE2_H_START_END 0x1d2f
|
||
|
#define VPP_SMOKE2_V_START_END 0x1d30
|
||
|
#define VPP_SMOKE3_H_START_END 0x1d31
|
||
|
#define VPP_SMOKE3_V_START_END 0x1d32
|
||
|
#define VPP_SCO_FIFO_CTRL 0x1d33
|
||
|
#define VPP_HSC_PHASE_CTRL1 0x1d34
|
||
|
#define VPP_HSC_INI_PAT_CTRL 0x1d35
|
||
|
#define VPP_VADJ_CTRL 0x1d40
|
||
|
#define VPP_VADJ1_Y 0x1d41
|
||
|
#define VPP_VADJ1_MA_MB 0x1d42
|
||
|
#define VPP_VADJ1_MC_MD 0x1d43
|
||
|
#define VPP_VADJ2_Y 0x1d44
|
||
|
#define VPP_VADJ2_MA_MB 0x1d45
|
||
|
#define VPP_VADJ2_MC_MD 0x1d46
|
||
|
#define VPP_HSHARP_CTRL 0x1d50
|
||
|
#define VPP_HSHARP_LUMA_THRESH01 0x1d51
|
||
|
#define VPP_HSHARP_LUMA_THRESH23 0x1d52
|
||
|
#define VPP_HSHARP_CHROMA_THRESH01 0x1d53
|
||
|
#define VPP_HSHARP_CHROMA_THRESH23 0x1d54
|
||
|
#define VPP_HSHARP_LUMA_GAIN 0x1d55
|
||
|
#define VPP_HSHARP_CHROMA_GAIN 0x1d56
|
||
|
#define VPP_MATRIX_PROBE_COLOR 0x1d5c
|
||
|
#define VPP_MATRIX_HL_COLOR 0x1d5d
|
||
|
#define VPP_MATRIX_PROBE_POS 0x1d5e
|
||
|
#define VPP_MATRIX_CTRL 0x1d5f
|
||
|
#define VPP_MATRIX_COEF00_01 0x1d60
|
||
|
#define VPP_MATRIX_COEF02_10 0x1d61
|
||
|
#define VPP_MATRIX_COEF11_12 0x1d62
|
||
|
#define VPP_MATRIX_COEF20_21 0x1d63
|
||
|
#define VPP_MATRIX_COEF22 0x1d64
|
||
|
#define VPP_MATRIX_OFFSET0_1 0x1d65
|
||
|
#define VPP_MATRIX_OFFSET2 0x1d66
|
||
|
#define VPP_MATRIX_PRE_OFFSET0_1 0x1d67
|
||
|
#define VPP_MATRIX_PRE_OFFSET2 0x1d68
|
||
|
#define VPP_DUMMY_DATA1 0x1d69
|
||
|
#define VPP_GAINOFF_CTRL0 0x1d6a
|
||
|
#define VPP_GAINOFF_CTRL1 0x1d6b
|
||
|
#define VPP_GAINOFF_CTRL2 0x1d6c
|
||
|
#define VPP_GAINOFF_CTRL3 0x1d6d
|
||
|
#define VPP_GAINOFF_CTRL4 0x1d6e
|
||
|
#define VPP_CHROMA_ADDR_PORT 0x1d70
|
||
|
#define VPP_CHROMA_DATA_PORT 0x1d71
|
||
|
#define VPP_GCLK_CTRL0 0x1d72
|
||
|
#define VPP_GCLK_CTRL1 0x1d73
|
||
|
#define VPP_SC_GCLK_CTRL 0x1d74
|
||
|
#define VPP_MISC1 0x1d76
|
||
|
#define VPP_BLACKEXT_CTRL 0x1d80
|
||
|
#define VPP_DNLP_CTRL_00 0x1d81
|
||
|
#define VPP_DNLP_CTRL_01 0x1d82
|
||
|
#define VPP_DNLP_CTRL_02 0x1d83
|
||
|
#define VPP_DNLP_CTRL_03 0x1d84
|
||
|
#define VPP_DNLP_CTRL_04 0x1d85
|
||
|
#define VPP_DNLP_CTRL_05 0x1d86
|
||
|
#define VPP_DNLP_CTRL_06 0x1d87
|
||
|
#define VPP_DNLP_CTRL_07 0x1d88
|
||
|
#define VPP_DNLP_CTRL_08 0x1d89
|
||
|
#define VPP_DNLP_CTRL_09 0x1d8a
|
||
|
#define VPP_DNLP_CTRL_10 0x1d8b
|
||
|
#define VPP_DNLP_CTRL_11 0x1d8c
|
||
|
#define VPP_DNLP_CTRL_12 0x1d8d
|
||
|
#define VPP_DNLP_CTRL_13 0x1d8e
|
||
|
#define VPP_DNLP_CTRL_14 0x1d8f
|
||
|
#define VPP_DNLP_CTRL_15 0x1d90
|
||
|
#define VPP_PEAKING_HGAIN 0x1d91
|
||
|
#define VPP_PEAKING_VGAIN 0x1d92
|
||
|
#define VPP_PEAKING_NLP_1 0x1d93
|
||
|
#define VPP_DOLBY_CTRL 0x1d93
|
||
|
#define VPP_PEAKING_NLP_2 0x1d94
|
||
|
#define VPP_PEAKING_NLP_3 0x1d95
|
||
|
#define VPP_PEAKING_NLP_4 0x1d96
|
||
|
#define VPP_PEAKING_NLP_5 0x1d97
|
||
|
#define VPP_SHARP_LIMIT 0x1d98
|
||
|
#define VPP_VLTI_CTRL 0x1d99
|
||
|
#define VPP_HLTI_CTRL 0x1d9a
|
||
|
#define VPP_CTI_CTRL 0x1d9b
|
||
|
#define VPP_BLUE_STRETCH_1 0x1d9c
|
||
|
#define VPP_BLUE_STRETCH_2 0x1d9d
|
||
|
#define VPP_BLUE_STRETCH_3 0x1d9e
|
||
|
#define VPP_CCORING_CTRL 0x1da0
|
||
|
#define VPP_VE_ENABLE_CTRL 0x1da1
|
||
|
#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2
|
||
|
#define VPP_VE_DEMO_CENTER_BAR 0x1da3
|
||
|
#define VPP_VE_H_V_SIZE 0x1da4
|
||
|
#define VPP_VDO_MEAS_CTRL 0x1da8
|
||
|
#define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9
|
||
|
#define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa
|
||
|
#define VPP_INPUT_CTRL 0x1dab
|
||
|
#define VPP_CTI_CTRL2 0x1dac
|
||
|
#define VPP_PEAKING_SAT_THD1 0x1dad
|
||
|
#define VPP_PEAKING_SAT_THD2 0x1dae
|
||
|
#define VPP_PEAKING_SAT_THD3 0x1daf
|
||
|
#define VPP_PEAKING_SAT_THD4 0x1db0
|
||
|
#define VPP_PEAKING_SAT_THD5 0x1db1
|
||
|
#define VPP_PEAKING_SAT_THD6 0x1db2
|
||
|
#define VPP_PEAKING_SAT_THD7 0x1db3
|
||
|
#define VPP_PEAKING_SAT_THD8 0x1db4
|
||
|
#define VPP_PEAKING_SAT_THD9 0x1db5
|
||
|
#define VPP_PEAKING_GAIN_ADD1 0x1db6
|
||
|
#define VPP_PEAKING_GAIN_ADD2 0x1db7
|
||
|
#define VPP_PEAKING_DNLP 0x1db8
|
||
|
#define VPP_SHARP_DEMO_WIN_CTRL1 0x1db9
|
||
|
#define VPP_SHARP_DEMO_WIN_CTRL2 0x1dba
|
||
|
#define VPP_FRONT_HLTI_CTRL 0x1dbb
|
||
|
#define VPP_FRONT_CTI_CTRL 0x1dbc
|
||
|
#define VPP_FRONT_CTI_CTRL2 0x1dbd
|
||
|
#define VPP_OSD_VSC_PHASE_STEP 0x1dc0
|
||
|
#define VPP_OSD_VSC_INI_PHASE 0x1dc1
|
||
|
#define VPP_OSD_VSC_CTRL0 0x1dc2
|
||
|
#define VPP_OSD_HSC_PHASE_STEP 0x1dc3
|
||
|
#define VPP_OSD_HSC_INI_PHASE 0x1dc4
|
||
|
#define VPP_OSD_HSC_CTRL0 0x1dc5
|
||
|
#define VPP_OSD_HSC_INI_PAT_CTRL 0x1dc6
|
||
|
#define VPP_OSD_SC_DUMMY_DATA 0x1dc7
|
||
|
#define VPP_OSD_SC_CTRL0 0x1dc8
|
||
|
#define VPP_OSD_SCI_WH_M1 0x1dc9
|
||
|
#define VPP_OSD_SCO_H_START_END 0x1dca
|
||
|
#define VPP_OSD_SCO_V_START_END 0x1dcb
|
||
|
#define VPP_OSD_SCALE_COEF_IDX 0x1dcc
|
||
|
#define VPP_OSD_SCALE_COEF 0x1dcd
|
||
|
#define VPP_INT_LINE_NUM 0x1dce
|
||
|
|
||
|
/* viu2 */
|
||
|
#define VIU2_ADDR_START 0x1e00
|
||
|
#define VIU2_ADDR_END 0x1eff
|
||
|
#define VIU2_SW_RESET 0x1e01
|
||
|
#define VIU2_OSD1_CTRL_STAT 0x1e10
|
||
|
#define VIU2_OSD1_CTRL_STAT2 0x1e2d
|
||
|
#define VIU2_OSD1_COLOR_ADDR 0x1e11
|
||
|
#define VIU2_OSD1_COLOR 0x1e12
|
||
|
#define VIU2_OSD1_TCOLOR_AG0 0x1e17
|
||
|
#define VIU2_OSD1_TCOLOR_AG1 0x1e18
|
||
|
#define VIU2_OSD1_TCOLOR_AG2 0x1e19
|
||
|
#define VIU2_OSD1_TCOLOR_AG3 0x1e1a
|
||
|
#define VIU2_OSD1_BLK0_CFG_W0 0x1e1b
|
||
|
#define VIU2_OSD1_BLK1_CFG_W0 0x1e1f
|
||
|
#define VIU2_OSD1_BLK2_CFG_W0 0x1e23
|
||
|
#define VIU2_OSD1_BLK3_CFG_W0 0x1e27
|
||
|
#define VIU2_OSD1_BLK0_CFG_W1 0x1e1c
|
||
|
#define VIU2_OSD1_BLK1_CFG_W1 0x1e20
|
||
|
#define VIU2_OSD1_BLK2_CFG_W1 0x1e24
|
||
|
#define VIU2_OSD1_BLK3_CFG_W1 0x1e28
|
||
|
#define VIU2_OSD1_BLK0_CFG_W2 0x1e1d
|
||
|
#define VIU2_OSD1_BLK1_CFG_W2 0x1e21
|
||
|
#define VIU2_OSD1_BLK2_CFG_W2 0x1e25
|
||
|
#define VIU2_OSD1_BLK3_CFG_W2 0x1e29
|
||
|
#define VIU2_OSD1_BLK0_CFG_W3 0x1e1e
|
||
|
#define VIU2_OSD1_BLK1_CFG_W3 0x1e22
|
||
|
#define VIU2_OSD1_BLK2_CFG_W3 0x1e26
|
||
|
#define VIU2_OSD1_BLK3_CFG_W3 0x1e2a
|
||
|
#define VIU2_OSD1_BLK0_CFG_W4 0x1e13
|
||
|
#define VIU2_OSD1_BLK1_CFG_W4 0x1e14
|
||
|
#define VIU2_OSD1_BLK2_CFG_W4 0x1e15
|
||
|
#define VIU2_OSD1_BLK3_CFG_W4 0x1e16
|
||
|
#define VIU2_OSD1_FIFO_CTRL_STAT 0x1e2b
|
||
|
#define VIU2_OSD1_TEST_RDDATA 0x1e2c
|
||
|
#define VIU2_OSD1_PROT_CTRL 0x1e2e
|
||
|
#define VIU2_OSD2_CTRL_STAT 0x1e30
|
||
|
#define VIU2_OSD2_CTRL_STAT2 0x1e4d
|
||
|
#define VIU2_OSD2_COLOR_ADDR 0x1e31
|
||
|
#define VIU2_OSD2_COLOR 0x1e32
|
||
|
#define VIU2_OSD2_HL1_H_START_END 0x1e33
|
||
|
#define VIU2_OSD2_HL1_V_START_END 0x1e34
|
||
|
#define VIU2_OSD2_HL2_H_START_END 0x1e35
|
||
|
#define VIU2_OSD2_HL2_V_START_END 0x1e36
|
||
|
#define VIU2_OSD2_TCOLOR_AG0 0x1e37
|
||
|
#define VIU2_OSD2_TCOLOR_AG1 0x1e38
|
||
|
#define VIU2_OSD2_TCOLOR_AG2 0x1e39
|
||
|
#define VIU2_OSD2_TCOLOR_AG3 0x1e3a
|
||
|
#define VIU2_OSD2_BLK0_CFG_W0 0x1e3b
|
||
|
#define VIU2_OSD2_BLK1_CFG_W0 0x1e3f
|
||
|
#define VIU2_OSD2_BLK2_CFG_W0 0x1e43
|
||
|
#define VIU2_OSD2_BLK3_CFG_W0 0x1e47
|
||
|
#define VIU2_OSD2_BLK0_CFG_W1 0x1e3c
|
||
|
#define VIU2_OSD2_BLK1_CFG_W1 0x1e40
|
||
|
#define VIU2_OSD2_BLK2_CFG_W1 0x1e44
|
||
|
#define VIU2_OSD2_BLK3_CFG_W1 0x1e48
|
||
|
#define VIU2_OSD2_BLK0_CFG_W2 0x1e3d
|
||
|
#define VIU2_OSD2_BLK1_CFG_W2 0x1e41
|
||
|
#define VIU2_OSD2_BLK2_CFG_W2 0x1e45
|
||
|
#define VIU2_OSD2_BLK3_CFG_W2 0x1e49
|
||
|
#define VIU2_OSD2_BLK0_CFG_W3 0x1e3e
|
||
|
#define VIU2_OSD2_BLK1_CFG_W3 0x1e42
|
||
|
#define VIU2_OSD2_BLK2_CFG_W3 0x1e46
|
||
|
#define VIU2_OSD2_BLK3_CFG_W3 0x1e4a
|
||
|
#define VIU2_OSD2_BLK0_CFG_W4 0x1e64
|
||
|
#define VIU2_OSD2_BLK1_CFG_W4 0x1e65
|
||
|
#define VIU2_OSD2_BLK2_CFG_W4 0x1e66
|
||
|
#define VIU2_OSD2_BLK3_CFG_W4 0x1e67
|
||
|
#define VIU2_OSD2_FIFO_CTRL_STAT 0x1e4b
|
||
|
#define VIU2_OSD2_TEST_RDDATA 0x1e4c
|
||
|
#define VIU2_OSD2_PROT_CTRL 0x1e4e
|
||
|
#define VIU2_VD1_IF0_GEN_REG 0x1e50
|
||
|
#define VIU2_VD1_IF0_CANVAS0 0x1e51
|
||
|
#define VIU2_VD1_IF0_CANVAS1 0x1e52
|
||
|
#define VIU2_VD1_IF0_LUMA_X0 0x1e53
|
||
|
#define VIU2_VD1_IF0_LUMA_Y0 0x1e54
|
||
|
#define VIU2_VD1_IF0_CHROMA_X0 0x1e55
|
||
|
#define VIU2_VD1_IF0_CHROMA_Y0 0x1e56
|
||
|
#define VIU2_VD1_IF0_LUMA_X1 0x1e57
|
||
|
#define VIU2_VD1_IF0_LUMA_Y1 0x1e58
|
||
|
#define VIU2_VD1_IF0_CHROMA_X1 0x1e59
|
||
|
#define VIU2_VD1_IF0_CHROMA_Y1 0x1e5a
|
||
|
#define VIU2_VD1_IF0_RPT_LOOP 0x1e5b
|
||
|
#define VIU2_VD1_IF0_LUMA0_RPT_PAT 0x1e5c
|
||
|
#define VIU2_VD1_IF0_CHROMA0_RPT_PAT 0x1e5d
|
||
|
#define VIU2_VD1_IF0_LUMA1_RPT_PAT 0x1e5e
|
||
|
#define VIU2_VD1_IF0_CHROMA1_RPT_PAT 0x1e5f
|
||
|
#define VIU2_VD1_IF0_LUMA_PSEL 0x1e60
|
||
|
#define VIU2_VD1_IF0_CHROMA_PSEL 0x1e61
|
||
|
#define VIU2_VD1_IF0_DUMMY_PIXEL 0x1e62
|
||
|
#define VIU2_VD1_IF0_LUMA_FIFO_SIZE 0x1e63
|
||
|
#define VIU2_VD1_IF0_RANGE_MAP_Y 0x1e6a
|
||
|
#define VIU2_VD1_IF0_RANGE_MAP_CB 0x1e6b
|
||
|
#define VIU2_VD1_IF0_RANGE_MAP_CR 0x1e6c
|
||
|
#define VIU2_VD1_IF0_GEN_REG2 0x1e6d
|
||
|
#define VIU2_VD1_IF0_PROT_CNTL 0x1e6e
|
||
|
#define VIU2_VD1_FMT_CTRL 0x1e68
|
||
|
#define VIU2_VD1_FMT_W 0x1e69
|
||
|
|
||
|
/* encode */
|
||
|
#define ENCP_VFIFO2VD_CTL 0x1b58
|
||
|
#define ENCP_VFIFO2VD_PIXEL_START 0x1b59
|
||
|
#define ENCP_VFIFO2VD_PIXEL_END 0x1b5a
|
||
|
#define ENCP_VFIFO2VD_LINE_TOP_START 0x1b5b
|
||
|
#define ENCP_VFIFO2VD_LINE_TOP_END 0x1b5c
|
||
|
#define ENCP_VFIFO2VD_LINE_BOT_START 0x1b5d
|
||
|
#define ENCP_VFIFO2VD_LINE_BOT_END 0x1b5e
|
||
|
#define VENC_SYNC_ROUTE 0x1b60
|
||
|
#define VENC_VIDEO_EXSRC 0x1b61
|
||
|
#define VENC_DVI_SETTING 0x1b62
|
||
|
#define VENC_C656_CTRL 0x1b63
|
||
|
#define VENC_UPSAMPLE_CTRL0 0x1b64
|
||
|
#define VENC_UPSAMPLE_CTRL1 0x1b65
|
||
|
#define VENC_UPSAMPLE_CTRL2 0x1b66
|
||
|
#define TCON_INVERT_CTL 0x1b67
|
||
|
#define VENC_VIDEO_PROG_MODE 0x1b68
|
||
|
#define VENC_ENCI_LINE 0x1b69
|
||
|
#define VENC_ENCI_PIXEL 0x1b6a
|
||
|
#define VENC_ENCP_LINE 0x1b6b
|
||
|
#define VENC_ENCP_PIXEL 0x1b6c
|
||
|
#define VENC_STATA 0x1b6d
|
||
|
#define VENC_INTCTRL 0x1b6e
|
||
|
#define VENC_INTFLAG 0x1b6f
|
||
|
#define VENC_VIDEO_TST_EN 0x1b70
|
||
|
#define VENC_VIDEO_TST_MDSEL 0x1b71
|
||
|
#define VENC_VIDEO_TST_Y 0x1b72
|
||
|
#define VENC_VIDEO_TST_CB 0x1b73
|
||
|
#define VENC_VIDEO_TST_CR 0x1b74
|
||
|
#define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75
|
||
|
#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76
|
||
|
#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77
|
||
|
#define VENC_VDAC_DACSEL0 0x1b78
|
||
|
#define VENC_VDAC_DACSEL1 0x1b79
|
||
|
#define VENC_VDAC_DACSEL2 0x1b7a
|
||
|
#define VENC_VDAC_DACSEL3 0x1b7b
|
||
|
#define VENC_VDAC_DACSEL4 0x1b7c
|
||
|
#define VENC_VDAC_DACSEL5 0x1b7d
|
||
|
#define VENC_VDAC_SETTING 0x1b7e
|
||
|
#define VENC_VDAC_TST_VAL 0x1b7f
|
||
|
#define VENC_VDAC_DAC0_GAINCTRL 0x1bf0
|
||
|
#define VENC_VDAC_DAC0_OFFSET 0x1bf1
|
||
|
#define VENC_VDAC_DAC1_GAINCTRL 0x1bf2
|
||
|
#define VENC_VDAC_DAC1_OFFSET 0x1bf3
|
||
|
#define VENC_VDAC_DAC2_GAINCTRL 0x1bf4
|
||
|
#define VENC_VDAC_DAC2_OFFSET 0x1bf5
|
||
|
#define VENC_VDAC_DAC3_GAINCTRL 0x1bf6
|
||
|
#define VENC_VDAC_DAC3_OFFSET 0x1bf7
|
||
|
#define VENC_VDAC_DAC4_GAINCTRL 0x1bf8
|
||
|
#define VENC_VDAC_DAC4_OFFSET 0x1bf9
|
||
|
#define VENC_VDAC_DAC5_GAINCTRL 0x1bfa
|
||
|
#define VENC_VDAC_DAC5_OFFSET 0x1bfb
|
||
|
#define VENC_VDAC_FIFO_CTRL 0x1bfc
|
||
|
#define ENCL_TCON_INVERT_CTL 0x1bfd
|
||
|
#define ENCP_VIDEO_EN 0x1b80
|
||
|
#define ENCP_VIDEO_SYNC_MODE 0x1b81
|
||
|
#define ENCP_MACV_EN 0x1b82
|
||
|
#define ENCP_VIDEO_Y_SCL 0x1b83
|
||
|
#define ENCP_VIDEO_PB_SCL 0x1b84
|
||
|
#define ENCP_VIDEO_PR_SCL 0x1b85
|
||
|
#define ENCP_VIDEO_SYNC_SCL 0x1b86
|
||
|
#define ENCP_VIDEO_MACV_SCL 0x1b87
|
||
|
#define ENCP_VIDEO_Y_OFFST 0x1b88
|
||
|
#define ENCP_VIDEO_PB_OFFST 0x1b89
|
||
|
#define ENCP_VIDEO_PR_OFFST 0x1b8a
|
||
|
#define ENCP_VIDEO_SYNC_OFFST 0x1b8b
|
||
|
#define ENCP_VIDEO_MACV_OFFST 0x1b8c
|
||
|
#define ENCP_VIDEO_MODE 0x1b8d
|
||
|
#define ENCP_VIDEO_MODE_ADV 0x1b8e
|
||
|
#define ENCP_DBG_PX_RST 0x1b90
|
||
|
#define ENCP_DBG_LN_RST 0x1b91
|
||
|
#define ENCP_DBG_PX_INT 0x1b92
|
||
|
#define ENCP_DBG_LN_INT 0x1b93
|
||
|
#define ENCP_VIDEO_YFP1_HTIME 0x1b94
|
||
|
#define ENCP_VIDEO_YFP2_HTIME 0x1b95
|
||
|
#define ENCP_VIDEO_YC_DLY 0x1b96
|
||
|
#define ENCP_VIDEO_MAX_PXCNT 0x1b97
|
||
|
#define ENCP_VIDEO_HSPULS_BEGIN 0x1b98
|
||
|
#define ENCP_VIDEO_HSPULS_END 0x1b99
|
||
|
#define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a
|
||
|
#define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b
|
||
|
#define ENCP_VIDEO_VSPULS_END 0x1b9c
|
||
|
#define ENCP_VIDEO_VSPULS_BLINE 0x1b9d
|
||
|
#define ENCP_VIDEO_VSPULS_ELINE 0x1b9e
|
||
|
#define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f
|
||
|
#define ENCP_VIDEO_EQPULS_END 0x1ba0
|
||
|
#define ENCP_VIDEO_EQPULS_BLINE 0x1ba1
|
||
|
#define ENCP_VIDEO_EQPULS_ELINE 0x1ba2
|
||
|
#define ENCP_VIDEO_HAVON_END 0x1ba3
|
||
|
#define ENCP_VIDEO_HAVON_BEGIN 0x1ba4
|
||
|
#define ENCP_VIDEO_VAVON_ELINE 0x1baf
|
||
|
#define ENCP_VIDEO_VAVON_BLINE 0x1ba6
|
||
|
#define ENCP_VIDEO_HSO_BEGIN 0x1ba7
|
||
|
#define ENCP_VIDEO_HSO_END 0x1ba8
|
||
|
#define ENCP_VIDEO_VSO_BEGIN 0x1ba9
|
||
|
#define ENCP_VIDEO_VSO_END 0x1baa
|
||
|
#define ENCP_VIDEO_VSO_BLINE 0x1bab
|
||
|
#define ENCP_VIDEO_VSO_ELINE 0x1bac
|
||
|
#define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad
|
||
|
#define ENCP_VIDEO_MAX_LNCNT 0x1bae
|
||
|
#define ENCP_VIDEO_SY_VAL 0x1bb0
|
||
|
#define ENCP_VIDEO_SY2_VAL 0x1bb1
|
||
|
#define ENCP_VIDEO_BLANKY_VAL 0x1bb2
|
||
|
#define ENCP_VIDEO_BLANKPB_VAL 0x1bb3
|
||
|
#define ENCP_VIDEO_BLANKPR_VAL 0x1bb4
|
||
|
#define ENCP_VIDEO_HOFFST 0x1bb5
|
||
|
#define ENCP_VIDEO_VOFFST 0x1bb6
|
||
|
#define ENCP_VIDEO_RGB_CTRL 0x1bb7
|
||
|
#define ENCP_VIDEO_FILT_CTRL 0x1bb8
|
||
|
#define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9
|
||
|
#define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba
|
||
|
#define ENCP_VIDEO_MATRIX_CB 0x1bbb
|
||
|
#define ENCP_VIDEO_MATRIX_CR 0x1bbc
|
||
|
#define ENCP_VIDEO_RGBIN_CTRL 0x1bbd
|
||
|
#define ENCP_MACV_BLANKY_VAL 0x1bc0
|
||
|
#define ENCP_MACV_MAXY_VAL 0x1bc1
|
||
|
#define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2
|
||
|
#define ENCP_MACV_PSSYNC_STRT 0x1bc3
|
||
|
#define ENCP_MACV_AGC_STRT 0x1bc4
|
||
|
#define ENCP_MACV_AGC_END 0x1bc5
|
||
|
#define ENCP_MACV_WAVE_END 0x1bc6
|
||
|
#define ENCP_MACV_STRTLINE 0x1bc7
|
||
|
#define ENCP_MACV_ENDLINE 0x1bc8
|
||
|
#define ENCP_MACV_TS_CNT_MAX_L 0x1bc9
|
||
|
#define ENCP_MACV_TS_CNT_MAX_H 0x1bca
|
||
|
#define ENCP_MACV_TIME_DOWN 0x1bcb
|
||
|
#define ENCP_MACV_TIME_LO 0x1bcc
|
||
|
#define ENCP_MACV_TIME_UP 0x1bcd
|
||
|
#define ENCP_MACV_TIME_RST 0x1bce
|
||
|
#define ENCP_VBI_CTRL 0x1bd0
|
||
|
#define ENCP_VBI_SETTING 0x1bd1
|
||
|
#define ENCP_VBI_BEGIN 0x1bd2
|
||
|
#define ENCP_VBI_WIDTH 0x1bd3
|
||
|
#define ENCP_VBI_HVAL 0x1bd4
|
||
|
#define ENCP_VBI_DATA0 0x1bd5
|
||
|
#define ENCP_VBI_DATA1 0x1bd6
|
||
|
#define C656_HS_ST 0x1be0
|
||
|
#define C656_HS_ED 0x1be1
|
||
|
#define C656_VS_LNST_E 0x1be2
|
||
|
#define C656_VS_LNST_O 0x1be3
|
||
|
#define C656_VS_LNED_E 0x1be4
|
||
|
#define C656_VS_LNED_O 0x1be5
|
||
|
#define C656_FS_LNST 0x1be6
|
||
|
#define C656_FS_LNED 0x1be7
|
||
|
#define ENCI_VIDEO_MODE 0x1b00
|
||
|
#define ENCI_VIDEO_MODE_ADV 0x1b01
|
||
|
#define ENCI_VIDEO_FSC_ADJ 0x1b02
|
||
|
#define ENCI_VIDEO_BRIGHT 0x1b03
|
||
|
#define ENCI_VIDEO_CONT 0x1b04
|
||
|
#define ENCI_VIDEO_SAT 0x1b05
|
||
|
#define ENCI_VIDEO_HUE 0x1b06
|
||
|
#define ENCI_VIDEO_SCH 0x1b07
|
||
|
#define ENCI_SYNC_MODE 0x1b08
|
||
|
#define ENCI_SYNC_CTRL 0x1b09
|
||
|
#define ENCI_SYNC_HSO_BEGIN 0x1b0a
|
||
|
#define ENCI_SYNC_HSO_END 0x1b0b
|
||
|
#define ENCI_SYNC_VSO_EVN 0x1b0c
|
||
|
#define ENCI_SYNC_VSO_ODD 0x1b0d
|
||
|
#define ENCI_SYNC_VSO_EVNLN 0x1b0e
|
||
|
#define ENCI_SYNC_VSO_ODDLN 0x1b0f
|
||
|
#define ENCI_SYNC_HOFFST 0x1b10
|
||
|
#define ENCI_SYNC_VOFFST 0x1b11
|
||
|
#define ENCI_SYNC_ADJ 0x1b12
|
||
|
#define ENCI_RGB_SETTING 0x1b13
|
||
|
#define ENCI_DE_H_BEGIN 0x1b16
|
||
|
#define ENCI_DE_H_END 0x1b17
|
||
|
#define ENCI_DE_V_BEGIN_EVEN 0x1b18
|
||
|
#define ENCI_DE_V_END_EVEN 0x1b19
|
||
|
#define ENCI_DE_V_BEGIN_ODD 0x1b1a
|
||
|
#define ENCI_DE_V_END_ODD 0x1b1b
|
||
|
#define ENCI_VBI_SETTING 0x1b20
|
||
|
#define ENCI_VBI_CCDT_EVN 0x1b21
|
||
|
#define ENCI_VBI_CCDT_ODD 0x1b22
|
||
|
#define ENCI_VBI_CC525_LN 0x1b23
|
||
|
#define ENCI_VBI_CC625_LN 0x1b24
|
||
|
#define ENCI_VBI_WSSDT 0x1b25
|
||
|
#define ENCI_VBI_WSS_LN 0x1b26
|
||
|
#define ENCI_VBI_CGMSDT_L 0x1b27
|
||
|
#define ENCI_VBI_CGMSDT_H 0x1b28
|
||
|
#define ENCI_VBI_CGMS_LN 0x1b29
|
||
|
#define ENCI_VBI_TTX_HTIME 0x1b2a
|
||
|
#define ENCI_VBI_TTX_LN 0x1b2b
|
||
|
#define ENCI_VBI_TTXDT0 0x1b2c
|
||
|
#define ENCI_VBI_TTXDT1 0x1b2d
|
||
|
#define ENCI_VBI_TTXDT2 0x1b2e
|
||
|
#define ENCI_VBI_TTXDT3 0x1b2f
|
||
|
#define ENCI_MACV_N0 0x1b30
|
||
|
#define ENCI_MACV_N1 0x1b31
|
||
|
#define ENCI_MACV_N2 0x1b32
|
||
|
#define ENCI_MACV_N3 0x1b33
|
||
|
#define ENCI_MACV_N4 0x1b34
|
||
|
#define ENCI_MACV_N5 0x1b35
|
||
|
#define ENCI_MACV_N6 0x1b36
|
||
|
#define ENCI_MACV_N7 0x1b37
|
||
|
#define ENCI_MACV_N8 0x1b38
|
||
|
#define ENCI_MACV_N9 0x1b39
|
||
|
#define ENCI_MACV_N10 0x1b3a
|
||
|
#define ENCI_MACV_N11 0x1b3b
|
||
|
#define ENCI_MACV_N12 0x1b3c
|
||
|
#define ENCI_MACV_N13 0x1b3d
|
||
|
#define ENCI_MACV_N14 0x1b3e
|
||
|
#define ENCI_MACV_N15 0x1b3f
|
||
|
#define ENCI_MACV_N16 0x1b40
|
||
|
#define ENCI_MACV_N17 0x1b41
|
||
|
#define ENCI_MACV_N18 0x1b42
|
||
|
#define ENCI_MACV_N19 0x1b43
|
||
|
#define ENCI_MACV_N20 0x1b44
|
||
|
#define ENCI_MACV_N21 0x1b45
|
||
|
#define ENCI_MACV_N22 0x1b46
|
||
|
#define ENCI_DBG_PX_RST 0x1b48
|
||
|
#define ENCI_DBG_FLDLN_RST 0x1b49
|
||
|
#define ENCI_DBG_PX_INT 0x1b4a
|
||
|
#define ENCI_DBG_FLDLN_INT 0x1b4b
|
||
|
#define ENCI_DBG_MAXPX 0x1b4c
|
||
|
#define ENCI_DBG_MAXLN 0x1b4d
|
||
|
#define ENCI_MACV_MAX_AMP 0x1b50
|
||
|
#define ENCI_MACV_PULSE_LO 0x1b51
|
||
|
#define ENCI_MACV_PULSE_HI 0x1b52
|
||
|
#define ENCI_MACV_BKP_MAX 0x1b53
|
||
|
#define ENCI_CFILT_CTRL 0x1b54
|
||
|
#define ENCI_CFILT7 0x1b55
|
||
|
#define ENCI_YC_DELAY 0x1b56
|
||
|
#define ENCI_VIDEO_EN 0x1b57
|
||
|
#define ENCI_DVI_HSO_BEGIN 0x1c00
|
||
|
#define ENCI_DVI_HSO_END 0x1c01
|
||
|
#define ENCI_DVI_VSO_BLINE_EVN 0x1c02
|
||
|
#define ENCI_DVI_VSO_BLINE_ODD 0x1c03
|
||
|
#define ENCI_DVI_VSO_ELINE_EVN 0x1c04
|
||
|
#define ENCI_DVI_VSO_ELINE_ODD 0x1c05
|
||
|
#define ENCI_DVI_VSO_BEGIN_EVN 0x1c06
|
||
|
#define ENCI_DVI_VSO_BEGIN_ODD 0x1c07
|
||
|
#define ENCI_DVI_VSO_END_EVN 0x1c08
|
||
|
#define ENCI_DVI_VSO_END_ODD 0x1c09
|
||
|
#define ENCI_CFILT_CTRL2 0x1c0a
|
||
|
#define ENCI_DACSEL_0 0x1c0b
|
||
|
#define ENCI_DACSEL_1 0x1c0c
|
||
|
#define ENCP_DACSEL_0 0x1c0d
|
||
|
#define ENCP_DACSEL_1 0x1c0e
|
||
|
#define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f
|
||
|
#define ENCI_TST_EN 0x1c10
|
||
|
#define ENCI_TST_MDSEL 0x1c11
|
||
|
#define ENCI_TST_Y 0x1c12
|
||
|
#define ENCI_TST_CB 0x1c13
|
||
|
#define ENCI_TST_CR 0x1c14
|
||
|
#define ENCI_TST_CLRBAR_STRT 0x1c15
|
||
|
#define ENCI_TST_CLRBAR_WIDTH 0x1c16
|
||
|
#define ENCI_TST_VDCNT_STSET 0x1c17
|
||
|
#define ENCI_VFIFO2VD_CTL 0x1c18
|
||
|
#define ENCI_VFIFO2VD_PIXEL_START 0x1c19
|
||
|
#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a
|
||
|
#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b
|
||
|
#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c
|
||
|
#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d
|
||
|
#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e
|
||
|
#define ENCI_VFIFO2VD_CTL2 0x1c1f
|
||
|
#define ENCT_VFIFO2VD_CTL 0x1c20
|
||
|
#define ENCT_VFIFO2VD_PIXEL_START 0x1c21
|
||
|
#define ENCT_VFIFO2VD_PIXEL_END 0x1c22
|
||
|
#define ENCT_VFIFO2VD_LINE_TOP_START 0x1c23
|
||
|
#define ENCT_VFIFO2VD_LINE_TOP_END 0x1c24
|
||
|
#define ENCT_VFIFO2VD_LINE_BOT_START 0x1c25
|
||
|
#define ENCT_VFIFO2VD_LINE_BOT_END 0x1c26
|
||
|
#define ENCT_VFIFO2VD_CTL2 0x1c27
|
||
|
#define ENCT_TST_EN 0x1c28
|
||
|
#define ENCT_TST_MDSEL 0x1c29
|
||
|
#define ENCT_TST_Y 0x1c2a
|
||
|
#define ENCT_TST_CB 0x1c2b
|
||
|
#define ENCT_TST_CR 0x1c2c
|
||
|
#define ENCT_TST_CLRBAR_STRT 0x1c2d
|
||
|
#define ENCT_TST_CLRBAR_WIDTH 0x1c2e
|
||
|
#define ENCT_TST_VDCNT_STSET 0x1c2f
|
||
|
#define ENCP_DVI_HSO_BEGIN 0x1c30
|
||
|
#define ENCP_DVI_HSO_END 0x1c31
|
||
|
#define ENCP_DVI_VSO_BLINE_EVN 0x1c32
|
||
|
#define ENCP_DVI_VSO_BLINE_ODD 0x1c33
|
||
|
#define ENCP_DVI_VSO_ELINE_EVN 0x1c34
|
||
|
#define ENCP_DVI_VSO_ELINE_ODD 0x1c35
|
||
|
#define ENCP_DVI_VSO_BEGIN_EVN 0x1c36
|
||
|
#define ENCP_DVI_VSO_BEGIN_ODD 0x1c37
|
||
|
#define ENCP_DVI_VSO_END_EVN 0x1c38
|
||
|
#define ENCP_DVI_VSO_END_ODD 0x1c39
|
||
|
#define ENCP_DE_H_BEGIN 0x1c3a
|
||
|
#define ENCP_DE_H_END 0x1c3b
|
||
|
#define ENCP_DE_V_BEGIN_EVEN 0x1c3c
|
||
|
#define ENCP_DE_V_END_EVEN 0x1c3d
|
||
|
#define ENCP_DE_V_BEGIN_ODD 0x1c3e
|
||
|
#define ENCP_DE_V_END_ODD 0x1c3f
|
||
|
#define ENCI_SYNC_LINE_LENGTH 0x1c40
|
||
|
#define ENCI_SYNC_PIXEL_EN 0x1c41
|
||
|
#define ENCI_SYNC_TO_LINE_EN 0x1c42
|
||
|
#define ENCI_SYNC_TO_PIXEL 0x1c43
|
||
|
#define ENCP_SYNC_LINE_LENGTH 0x1c44
|
||
|
#define ENCP_SYNC_PIXEL_EN 0x1c45
|
||
|
#define ENCP_SYNC_TO_LINE_EN 0x1c46
|
||
|
#define ENCP_SYNC_TO_PIXEL 0x1c47
|
||
|
#define ENCT_SYNC_LINE_LENGTH 0x1c48
|
||
|
#define ENCT_SYNC_PIXEL_EN 0x1c49
|
||
|
#define ENCT_SYNC_TO_LINE_EN 0x1c4a
|
||
|
#define ENCT_SYNC_TO_PIXEL 0x1c4b
|
||
|
#define ENCL_SYNC_LINE_LENGTH 0x1c4c
|
||
|
#define ENCL_SYNC_PIXEL_EN 0x1c4d
|
||
|
#define ENCL_SYNC_TO_LINE_EN 0x1c4e
|
||
|
#define ENCL_SYNC_TO_PIXEL 0x1c4f
|
||
|
#define ENCP_VFIFO2VD_CTL2 0x1c50
|
||
|
#define VENC_DVI_SETTING_MORE 0x1c51
|
||
|
#define VENC_VDAC_DAC4_FILT_CTRL0 0x1c54
|
||
|
#define VENC_VDAC_DAC4_FILT_CTRL1 0x1c55
|
||
|
#define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56
|
||
|
#define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57
|
||
|
#define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58
|
||
|
#define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59
|
||
|
#define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a
|
||
|
#define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b
|
||
|
#define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c
|
||
|
#define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d
|
||
|
#define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e
|
||
|
#define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f
|
||
|
#define ENCT_VIDEO_EN 0x1c60
|
||
|
#define ENCT_VIDEO_Y_SCL 0x1c61
|
||
|
#define ENCT_VIDEO_PB_SCL 0x1c62
|
||
|
#define ENCT_VIDEO_PR_SCL 0x1c63
|
||
|
#define ENCT_VIDEO_Y_OFFST 0x1c64
|
||
|
#define ENCT_VIDEO_PB_OFFST 0x1c65
|
||
|
#define ENCT_VIDEO_PR_OFFST 0x1c66
|
||
|
#define ENCT_VIDEO_MODE 0x1c67
|
||
|
#define ENCT_VIDEO_MODE_ADV 0x1c68
|
||
|
#define ENCT_DBG_PX_RST 0x1c69
|
||
|
#define ENCT_DBG_LN_RST 0x1c6a
|
||
|
#define ENCT_DBG_PX_INT 0x1c6b
|
||
|
#define ENCT_DBG_LN_INT 0x1c6c
|
||
|
#define ENCT_VIDEO_YFP1_HTIME 0x1c6d
|
||
|
#define ENCT_VIDEO_YFP2_HTIME 0x1c6e
|
||
|
#define ENCT_VIDEO_YC_DLY 0x1c6f
|
||
|
#define ENCT_VIDEO_MAX_PXCNT 0x1c70
|
||
|
#define ENCT_VIDEO_HAVON_END 0x1c71
|
||
|
#define ENCT_VIDEO_HAVON_BEGIN 0x1c72
|
||
|
#define ENCT_VIDEO_VAVON_ELINE 0x1c73
|
||
|
#define ENCT_VIDEO_VAVON_BLINE 0x1c74
|
||
|
#define ENCT_VIDEO_HSO_BEGIN 0x1c75
|
||
|
#define ENCT_VIDEO_HSO_END 0x1c76
|
||
|
#define ENCT_VIDEO_VSO_BEGIN 0x1c77
|
||
|
#define ENCT_VIDEO_VSO_END 0x1c78
|
||
|
#define ENCT_VIDEO_VSO_BLINE 0x1c79
|
||
|
#define ENCT_VIDEO_VSO_ELINE 0x1c7a
|
||
|
#define ENCT_VIDEO_MAX_LNCNT 0x1c7b
|
||
|
#define ENCT_VIDEO_BLANKY_VAL 0x1c7c
|
||
|
#define ENCT_VIDEO_BLANKPB_VAL 0x1c7d
|
||
|
#define ENCT_VIDEO_BLANKPR_VAL 0x1c7e
|
||
|
#define ENCT_VIDEO_HOFFST 0x1c7f
|
||
|
#define ENCT_VIDEO_VOFFST 0x1c80
|
||
|
#define ENCT_VIDEO_RGB_CTRL 0x1c81
|
||
|
#define ENCT_VIDEO_FILT_CTRL 0x1c82
|
||
|
#define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c83
|
||
|
#define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c84
|
||
|
#define ENCT_VIDEO_MATRIX_CB 0x1c85
|
||
|
#define ENCT_VIDEO_MATRIX_CR 0x1c86
|
||
|
#define ENCT_VIDEO_RGBIN_CTRL 0x1c87
|
||
|
#define ENCT_MAX_LINE_SWITCH_POINT 0x1c88
|
||
|
#define ENCT_DACSEL_0 0x1c89
|
||
|
#define ENCT_DACSEL_1 0x1c8a
|
||
|
#define ENCL_VFIFO2VD_CTL 0x1c90
|
||
|
#define ENCL_VFIFO2VD_PIXEL_START 0x1c91
|
||
|
#define ENCL_VFIFO2VD_PIXEL_END 0x1c92
|
||
|
#define ENCL_VFIFO2VD_LINE_TOP_START 0x1c93
|
||
|
#define ENCL_VFIFO2VD_LINE_TOP_END 0x1c94
|
||
|
#define ENCL_VFIFO2VD_LINE_BOT_START 0x1c95
|
||
|
#define ENCL_VFIFO2VD_LINE_BOT_END 0x1c96
|
||
|
#define ENCL_VFIFO2VD_CTL2 0x1c97
|
||
|
#define ENCL_TST_EN 0x1c98
|
||
|
#define ENCL_TST_MDSEL 0x1c99
|
||
|
#define ENCL_TST_Y 0x1c9a
|
||
|
#define ENCL_TST_CB 0x1c9b
|
||
|
#define ENCL_TST_CR 0x1c9c
|
||
|
#define ENCL_TST_CLRBAR_STRT 0x1c9d
|
||
|
#define ENCL_TST_CLRBAR_WIDTH 0x1c9e
|
||
|
#define ENCL_TST_VDCNT_STSET 0x1c9f
|
||
|
#define ENCL_VIDEO_EN 0x1ca0
|
||
|
#define ENCL_VIDEO_Y_SCL 0x1ca1
|
||
|
#define ENCL_VIDEO_PB_SCL 0x1ca2
|
||
|
#define ENCL_VIDEO_PR_SCL 0x1ca3
|
||
|
#define ENCL_VIDEO_Y_OFFST 0x1ca4
|
||
|
#define ENCL_VIDEO_PB_OFFST 0x1ca5
|
||
|
#define ENCL_VIDEO_PR_OFFST 0x1ca6
|
||
|
#define ENCL_VIDEO_MODE 0x1ca7
|
||
|
#define ENCL_VIDEO_MODE_ADV 0x1ca8
|
||
|
#define ENCL_DBG_PX_RST 0x1ca9
|
||
|
#define ENCL_DBG_LN_RST 0x1caa
|
||
|
#define ENCL_DBG_PX_INT 0x1cab
|
||
|
#define ENCL_DBG_LN_INT 0x1cac
|
||
|
#define ENCL_VIDEO_YFP1_HTIME 0x1cad
|
||
|
#define ENCL_VIDEO_YFP2_HTIME 0x1cae
|
||
|
#define ENCL_VIDEO_YC_DLY 0x1caf
|
||
|
#define ENCL_VIDEO_MAX_PXCNT 0x1cb0
|
||
|
#define ENCL_VIDEO_HAVON_END 0x1cb1
|
||
|
#define ENCL_VIDEO_HAVON_BEGIN 0x1cb2
|
||
|
#define ENCL_VIDEO_VAVON_ELINE 0x1cb3
|
||
|
#define ENCL_VIDEO_VAVON_BLINE 0x1cb4
|
||
|
#define ENCL_VIDEO_HSO_BEGIN 0x1cb5
|
||
|
#define ENCL_VIDEO_HSO_END 0x1cb6
|
||
|
#define ENCL_VIDEO_VSO_BEGIN 0x1cb7
|
||
|
#define ENCL_VIDEO_VSO_END 0x1cb8
|
||
|
#define ENCL_VIDEO_VSO_BLINE 0x1cb9
|
||
|
#define ENCL_VIDEO_VSO_ELINE 0x1cba
|
||
|
#define ENCL_VIDEO_MAX_LNCNT 0x1cbb
|
||
|
#define ENCL_VIDEO_BLANKY_VAL 0x1cbc
|
||
|
#define ENCL_VIDEO_BLANKPB_VAL 0x1cbd
|
||
|
#define ENCL_VIDEO_BLANKPR_VAL 0x1cbe
|
||
|
#define ENCL_VIDEO_HOFFST 0x1cbf
|
||
|
#define ENCL_VIDEO_VOFFST 0x1cc0
|
||
|
#define ENCL_VIDEO_RGB_CTRL 0x1cc1
|
||
|
#define ENCL_VIDEO_FILT_CTRL 0x1cc2
|
||
|
#define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3
|
||
|
#define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4
|
||
|
#define ENCL_VIDEO_MATRIX_CB 0x1cc5
|
||
|
#define ENCL_VIDEO_MATRIX_CR 0x1cc6
|
||
|
#define ENCL_VIDEO_RGBIN_CTRL 0x1cc7
|
||
|
#define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8
|
||
|
#define ENCL_DACSEL_0 0x1cc9
|
||
|
#define ENCL_DACSEL_1 0x1cca
|
||
|
#define RDMA_AHB_START_ADDR_MAN 0x1100
|
||
|
#define RDMA_AHB_END_ADDR_MAN 0x1101
|
||
|
#define RDMA_AHB_START_ADDR_1 0x1102
|
||
|
#define RDMA_AHB_END_ADDR_1 0x1103
|
||
|
#define RDMA_AHB_START_ADDR_2 0x1104
|
||
|
#define RDMA_AHB_END_ADDR_2 0x1105
|
||
|
#define RDMA_AHB_START_ADDR_3 0x1106
|
||
|
#define RDMA_AHB_END_ADDR_3 0x1107
|
||
|
#define RDMA_AHB_START_ADDR_4 0x1108
|
||
|
#define RDMA_AHB_END_ADDR_4 0x1109
|
||
|
#define RDMA_AHB_START_ADDR_5 0x110a
|
||
|
#define RDMA_AHB_END_ADDR_5 0x110b
|
||
|
#define RDMA_AHB_START_ADDR_6 0x110c
|
||
|
#define RDMA_AHB_END_ADDR_6 0x110d
|
||
|
#define RDMA_AHB_START_ADDR_7 0x110e
|
||
|
#define RDMA_AHB_END_ADDR_7 0x110f
|
||
|
#define RDMA_ACCESS_AUTO 0x1110
|
||
|
#define RDMA_ACCESS_AUTO2 0x1111
|
||
|
#define RDMA_ACCESS_AUTO3 0x1112
|
||
|
#define RDMA_ACCESS_MAN 0x1113
|
||
|
#define RDMA_CTRL 0x1114
|
||
|
#define RDMA_STATUS 0x1115
|
||
|
#define RDMA_STATUS2 0x1116
|
||
|
#define RDMA_STATUS3 0x1117
|
||
|
#define L_GAMMA_CNTL_PORT 0x1400
|
||
|
#define L_GAMMA_DATA_PORT 0x1401
|
||
|
#define L_GAMMA_ADDR_PORT 0x1402
|
||
|
#define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403
|
||
|
#define L_RGB_BASE_ADDR 0x1405
|
||
|
#define L_RGB_COEFF_ADDR 0x1406
|
||
|
#define L_POL_CNTL_ADDR 0x1407
|
||
|
#define L_DITH_CNTL_ADDR 0x1408
|
||
|
#define L_GAMMA_PROBE_CTRL 0x1409
|
||
|
#define L_GAMMA_PROBE_COLOR_L 0x140a
|
||
|
#define L_GAMMA_PROBE_COLOR_H 0x140b
|
||
|
#define L_GAMMA_PROBE_HL_COLOR 0x140c
|
||
|
#define L_GAMMA_PROBE_POS_X 0x140d
|
||
|
#define L_GAMMA_PROBE_POS_Y 0x140e
|
||
|
#define L_STH1_HS_ADDR 0x1410
|
||
|
#define L_STH1_HE_ADDR 0x1411
|
||
|
#define L_STH1_VS_ADDR 0x1412
|
||
|
#define L_STH1_VE_ADDR 0x1413
|
||
|
#define L_STH2_HS_ADDR 0x1414
|
||
|
#define L_STH2_HE_ADDR 0x1415
|
||
|
#define L_STH2_VS_ADDR 0x1416
|
||
|
#define L_STH2_VE_ADDR 0x1417
|
||
|
#define L_OEH_HS_ADDR 0x1418
|
||
|
#define L_OEH_HE_ADDR 0x1419
|
||
|
#define L_OEH_VS_ADDR 0x141a
|
||
|
#define L_OEH_VE_ADDR 0x141b
|
||
|
#define L_VCOM_HSWITCH_ADDR 0x141c
|
||
|
#define L_VCOM_VS_ADDR 0x141d
|
||
|
#define L_VCOM_VE_ADDR 0x141e
|
||
|
#define L_CPV1_HS_ADDR 0x141f
|
||
|
#define L_CPV1_HE_ADDR 0x1420
|
||
|
#define L_CPV1_VS_ADDR 0x1421
|
||
|
#define L_CPV1_VE_ADDR 0x1422
|
||
|
#define L_CPV2_HS_ADDR 0x1423
|
||
|
#define L_CPV2_HE_ADDR 0x1424
|
||
|
#define L_CPV2_VS_ADDR 0x1425
|
||
|
#define L_CPV2_VE_ADDR 0x1426
|
||
|
#define L_STV1_HS_ADDR 0x1427
|
||
|
#define L_STV1_HE_ADDR 0x1428
|
||
|
#define L_STV1_VS_ADDR 0x1429
|
||
|
#define L_STV1_VE_ADDR 0x142a
|
||
|
#define L_STV2_HS_ADDR 0x142b
|
||
|
#define L_STV2_HE_ADDR 0x142c
|
||
|
#define L_STV2_VS_ADDR 0x142d
|
||
|
#define L_STV2_VE_ADDR 0x142e
|
||
|
#define L_OEV1_HS_ADDR 0x142f
|
||
|
#define L_OEV1_HE_ADDR 0x1430
|
||
|
#define L_OEV1_VS_ADDR 0x1431
|
||
|
#define L_OEV1_VE_ADDR 0x1432
|
||
|
#define L_OEV2_HS_ADDR 0x1433
|
||
|
#define L_OEV2_HE_ADDR 0x1434
|
||
|
#define L_OEV2_VS_ADDR 0x1435
|
||
|
#define L_OEV2_VE_ADDR 0x1436
|
||
|
#define L_OEV3_HS_ADDR 0x1437
|
||
|
#define L_OEV3_HE_ADDR 0x1438
|
||
|
#define L_OEV3_VS_ADDR 0x1439
|
||
|
#define L_OEV3_VE_ADDR 0x143a
|
||
|
#define L_LCD_PWR_ADDR 0x143b
|
||
|
#define L_LCD_PWM0_LO_ADDR 0x143c
|
||
|
#define L_LCD_PWM0_HI_ADDR 0x143d
|
||
|
#define L_LCD_PWM1_LO_ADDR 0x143e
|
||
|
#define L_LCD_PWM1_HI_ADDR 0x143f
|
||
|
#define L_INV_CNT_ADDR 0x1440
|
||
|
#define L_TCON_MISC_SEL_ADDR 0x1441
|
||
|
#define L_DUAL_PORT_CNTL_ADDR 0x1442
|
||
|
#define MLVDS_CLK_CTL1_HI 0x1443
|
||
|
#define MLVDS_CLK_CTL1_LO 0x1444
|
||
|
#define L_TCON_DOUBLE_CTL 0x1449
|
||
|
#define L_TCON_PATTERN_HI 0x144a
|
||
|
#define L_TCON_PATTERN_LO 0x144b
|
||
|
#define LDIM_BL_ADDR_PORT 0x144e
|
||
|
#define LDIM_BL_DATA_PORT 0x144f
|
||
|
#define L_DE_HS_ADDR 0x1451
|
||
|
#define L_DE_HE_ADDR 0x1452
|
||
|
#define L_DE_VS_ADDR 0x1453
|
||
|
#define L_DE_VE_ADDR 0x1454
|
||
|
#define L_HSYNC_HS_ADDR 0x1455
|
||
|
#define L_HSYNC_HE_ADDR 0x1456
|
||
|
#define L_HSYNC_VS_ADDR 0x1457
|
||
|
#define L_HSYNC_VE_ADDR 0x1458
|
||
|
#define L_VSYNC_HS_ADDR 0x1459
|
||
|
#define L_VSYNC_HE_ADDR 0x145a
|
||
|
#define L_VSYNC_VS_ADDR 0x145b
|
||
|
#define L_VSYNC_VE_ADDR 0x145c
|
||
|
#define L_LCD_MCU_CTL 0x145d
|
||
|
#define DUAL_MLVDS_CTL 0x1460
|
||
|
#define DUAL_MLVDS_LINE_START 0x1461
|
||
|
#define DUAL_MLVDS_LINE_END 0x1462
|
||
|
#define DUAL_MLVDS_PIXEL_W_START_L 0x1463
|
||
|
#define DUAL_MLVDS_PIXEL_W_END_L 0x1464
|
||
|
#define DUAL_MLVDS_PIXEL_W_START_R 0x1465
|
||
|
#define DUAL_MLVDS_PIXEL_W_END_R 0x1466
|
||
|
#define DUAL_MLVDS_PIXEL_R_START_L 0x1467
|
||
|
#define DUAL_MLVDS_PIXEL_R_CNT_L 0x1468
|
||
|
#define DUAL_MLVDS_PIXEL_R_START_R 0x1469
|
||
|
#define DUAL_MLVDS_PIXEL_R_CNT_R 0x146a
|
||
|
#define V_INVERSION_PIXEL 0x1470
|
||
|
#define V_INVERSION_LINE 0x1471
|
||
|
#define V_INVERSION_CONTROL 0x1472
|
||
|
#define MLVDS2_CONTROL 0x1474
|
||
|
#define MLVDS2_CONFIG_HI 0x1475
|
||
|
#define MLVDS2_CONFIG_LO 0x1476
|
||
|
#define MLVDS2_DUAL_GATE_WR_START 0x1477
|
||
|
#define MLVDS2_DUAL_GATE_WR_END 0x1478
|
||
|
#define MLVDS2_DUAL_GATE_RD_START 0x1479
|
||
|
#define MLVDS2_DUAL_GATE_RD_END 0x147a
|
||
|
#define MLVDS2_SECOND_RESET_CTL 0x147b
|
||
|
#define MLVDS2_DUAL_GATE_CTL_HI 0x147c
|
||
|
#define MLVDS2_DUAL_GATE_CTL_LO 0x147d
|
||
|
#define MLVDS2_RESET_CONFIG_HI 0x147e
|
||
|
#define MLVDS2_RESET_CONFIG_LO 0x147f
|
||
|
#define GAMMA_CNTL_PORT 0x1480
|
||
|
#define GAMMA_DATA_PORT 0x1481
|
||
|
#define GAMMA_ADDR_PORT 0x1482
|
||
|
#define GAMMA_VCOM_HSWITCH_ADDR 0x1483
|
||
|
#define RGB_BASE_ADDR 0x1485
|
||
|
#define RGB_COEFF_ADDR 0x1486
|
||
|
#define POL_CNTL_ADDR 0x1487
|
||
|
#define DITH_CNTL_ADDR 0x1488
|
||
|
#define GAMMA_PROBE_CTRL 0x1489
|
||
|
#define GAMMA_PROBE_COLOR_L 0x148a
|
||
|
#define GAMMA_PROBE_COLOR_H 0x148b
|
||
|
#define GAMMA_PROBE_HL_COLOR 0x148c
|
||
|
#define GAMMA_PROBE_POS_X 0x148d
|
||
|
#define GAMMA_PROBE_POS_Y 0x148e
|
||
|
#define STH1_HS_ADDR 0x1490
|
||
|
#define STH1_HE_ADDR 0x1491
|
||
|
#define STH1_VS_ADDR 0x1492
|
||
|
#define STH1_VE_ADDR 0x1493
|
||
|
#define STH2_HS_ADDR 0x1494
|
||
|
#define STH2_HE_ADDR 0x1495
|
||
|
#define STH2_VS_ADDR 0x1496
|
||
|
#define STH2_VE_ADDR 0x1497
|
||
|
#define OEH_HS_ADDR 0x1498
|
||
|
#define OEH_HE_ADDR 0x1499
|
||
|
#define OEH_VS_ADDR 0x149a
|
||
|
#define OEH_VE_ADDR 0x149b
|
||
|
#define VCOM_HSWITCH_ADDR 0x149c
|
||
|
#define VCOM_VS_ADDR 0x149d
|
||
|
#define VCOM_VE_ADDR 0x149e
|
||
|
#define CPV1_HS_ADDR 0x149f
|
||
|
#define CPV1_HE_ADDR 0x14a0
|
||
|
#define CPV1_VS_ADDR 0x14a1
|
||
|
#define CPV1_VE_ADDR 0x14a2
|
||
|
#define CPV2_HS_ADDR 0x14a3
|
||
|
#define CPV2_HE_ADDR 0x14a4
|
||
|
#define CPV2_VS_ADDR 0x14a5
|
||
|
#define CPV2_VE_ADDR 0x14a6
|
||
|
#define STV1_HS_ADDR 0x14a7
|
||
|
#define STV1_HE_ADDR 0x14a8
|
||
|
#define STV1_VS_ADDR 0x14a9
|
||
|
#define STV1_VE_ADDR 0x14aa
|
||
|
#define STV2_HS_ADDR 0x14ab
|
||
|
#define STV2_HE_ADDR 0x14ac
|
||
|
#define STV2_VS_ADDR 0x14ad
|
||
|
#define STV2_VE_ADDR 0x14ae
|
||
|
#define OEV1_HS_ADDR 0x14af
|
||
|
#define OEV1_HE_ADDR 0x14b0
|
||
|
#define OEV1_VS_ADDR 0x14b1
|
||
|
#define OEV1_VE_ADDR 0x14b2
|
||
|
#define OEV2_HS_ADDR 0x14b3
|
||
|
#define OEV2_HE_ADDR 0x14b4
|
||
|
#define OEV2_VS_ADDR 0x14b5
|
||
|
#define OEV2_VE_ADDR 0x14b6
|
||
|
#define OEV3_HS_ADDR 0x14b7
|
||
|
#define OEV3_HE_ADDR 0x14b8
|
||
|
#define OEV3_VS_ADDR 0x14b9
|
||
|
#define OEV3_VE_ADDR 0x14ba
|
||
|
#define LCD_PWR_ADDR 0x14bb
|
||
|
#define LCD_PWM0_LO_ADDR 0x14bc
|
||
|
#define LCD_PWM0_HI_ADDR 0x14bd
|
||
|
#define LCD_PWM1_LO_ADDR 0x14be
|
||
|
#define LCD_PWM1_HI_ADDR 0x14bf
|
||
|
#define INV_CNT_ADDR 0x14c0
|
||
|
#define TCON_MISC_SEL_ADDR 0x14c1
|
||
|
#define DUAL_PORT_CNTL_ADDR 0x14c2
|
||
|
#define MLVDS_CONTROL 0x14c3
|
||
|
#define MLVDS_RESET_PATTERN_HI 0x14c4
|
||
|
#define MLVDS_RESET_PATTERN_LO 0x14c5
|
||
|
#define MLVDS_RESET_PATTERN_EXT 0x14c6
|
||
|
#define MLVDS_CONFIG_HI 0x14c7
|
||
|
#define MLVDS_CONFIG_LO 0x14c8
|
||
|
#define TCON_DOUBLE_CTL 0x14c9
|
||
|
#define TCON_PATTERN_HI 0x14ca
|
||
|
#define TCON_PATTERN_LO 0x14cb
|
||
|
#define TCON_CONTROL_HI 0x14cc
|
||
|
#define TCON_CONTROL_LO 0x14cd
|
||
|
#define LVDS_BLANK_DATA_HI 0x14ce
|
||
|
#define LVDS_BLANK_DATA_LO 0x14cf
|
||
|
#define LVDS_PACK_CNTL_ADDR 0x14d0
|
||
|
#define DE_HS_ADDR 0x14d1
|
||
|
#define DE_HE_ADDR 0x14d2
|
||
|
#define DE_VS_ADDR 0x14d3
|
||
|
#define DE_VE_ADDR 0x14d4
|
||
|
#define HSYNC_HS_ADDR 0x14d5
|
||
|
#define HSYNC_HE_ADDR 0x14d6
|
||
|
#define HSYNC_VS_ADDR 0x14d7
|
||
|
#define HSYNC_VE_ADDR 0x14d8
|
||
|
#define VSYNC_HS_ADDR 0x14d9
|
||
|
#define VSYNC_HE_ADDR 0x14da
|
||
|
#define VSYNC_VS_ADDR 0x14db
|
||
|
#define VSYNC_VE_ADDR 0x14dc
|
||
|
#define LCD_MCU_CTL 0x14dd
|
||
|
#define LCD_MCU_DATA_0 0x14de
|
||
|
#define LCD_MCU_DATA_1 0x14df
|
||
|
#define LVDS_GEN_CNTL 0x14e0
|
||
|
#define LVDS_PHY_CNTL0 0x14e1
|
||
|
#define LVDS_PHY_CNTL1 0x14e2
|
||
|
#define LVDS_PHY_CNTL2 0x14e3
|
||
|
#define LVDS_PHY_CNTL3 0x14e4
|
||
|
#define LVDS_PHY_CNTL4 0x14e5
|
||
|
#define LVDS_PHY_CNTL5 0x14e6
|
||
|
#define LVDS_SRG_TEST 0x14e8
|
||
|
#define LVDS_BIST_MUX0 0x14e9
|
||
|
#define LVDS_BIST_MUX1 0x14ea
|
||
|
#define LVDS_BIST_FIXED0 0x14eb
|
||
|
#define LVDS_BIST_FIXED1 0x14ec
|
||
|
#define LVDS_BIST_CNTL0 0x14ed
|
||
|
#define LVDS_CLKB_CLKA 0x14ee
|
||
|
#define LVDS_PHY_CLK_CNTL 0x14ef
|
||
|
#define LVDS_SER_EN 0x14f0
|
||
|
#define LVDS_PHY_CNTL6 0x14f1
|
||
|
#define LVDS_PHY_CNTL7 0x14f2
|
||
|
#define LVDS_PHY_CNTL8 0x14f3
|
||
|
#define MLVDS_CLK_CTL0_HI 0x14f4
|
||
|
#define MLVDS_CLK_CTL0_LO 0x14f5
|
||
|
#define MLVDS_DUAL_GATE_WR_START 0x14f6
|
||
|
#define MLVDS_DUAL_GATE_WR_END 0x14f7
|
||
|
#define MLVDS_DUAL_GATE_RD_START 0x14f8
|
||
|
#define MLVDS_DUAL_GATE_RD_END 0x14f9
|
||
|
#define MLVDS_SECOND_RESET_CTL 0x14fa
|
||
|
#define MLVDS_DUAL_GATE_CTL_HI 0x14fb
|
||
|
#define MLVDS_DUAL_GATE_CTL_LO 0x14fc
|
||
|
#define MLVDS_RESET_CONFIG_HI 0x14fd
|
||
|
#define MLVDS_RESET_CONFIG_LO 0x14fe
|
||
|
#define VPU_OSD1_MMC_CTRL 0x2701
|
||
|
#define VPU_OSD2_MMC_CTRL 0x2702
|
||
|
#define VPU_VD1_MMC_CTRL 0x2703
|
||
|
#define VPU_VD2_MMC_CTRL 0x2704
|
||
|
#define VPU_DI_IF1_MMC_CTRL 0x2705
|
||
|
#define VPU_DI_MEM_MMC_CTRL 0x2706
|
||
|
#define VPU_DI_INP_MMC_CTRL 0x2707
|
||
|
#define VPU_DI_MTNRD_MMC_CTRL 0x2708
|
||
|
#define VPU_DI_CHAN2_MMC_CTRL 0x2709
|
||
|
#define VPU_DI_MTNWR_MMC_CTRL 0x270a
|
||
|
#define VPU_DI_NRWR_MMC_CTRL 0x270b
|
||
|
#define VPU_DI_DIWR_MMC_CTRL 0x270c
|
||
|
#define VPU_VDIN0_MMC_CTRL 0x270d
|
||
|
#define VPU_VDIN1_MMC_CTRL 0x270e
|
||
|
#define VPU_BT656_MMC_CTRL 0x270f
|
||
|
#define VPU_TVD3D_MMC_CTRL 0x2710
|
||
|
#define VPU_TVDVBI_MMC_CTRL 0x2711
|
||
|
#define VPU_TVDVBI_VSLATCH_ADDR 0x2712
|
||
|
#define VPU_TVDVBI_WRRSP_ADDR 0x2713
|
||
|
#define VPU_VDIN_PRE_ARB_CTRL 0x2714
|
||
|
#define VPU_VDISP_PRE_ARB_CTRL 0x2715
|
||
|
#define VPU_VPUARB2_PRE_ARB_CTRL 0x2716
|
||
|
#define VPU_OSD3_MMC_CTRL 0x2717
|
||
|
#define VPU_OSD4_MMC_CTRL 0x2718
|
||
|
#define VPU_VD3_MMC_CTRL 0x2719
|
||
|
#define VPU_VIU_VENC_MUX_CTRL 0x271a
|
||
|
#define VIU1_SEL_VENC_MASK 0x3
|
||
|
#define VIU1_SEL_VENC_ENCL 0
|
||
|
#define VIU1_SEL_VENC_ENCI 1
|
||
|
#define VIU1_SEL_VENC_ENCP 2
|
||
|
#define VIU1_SEL_VENC_ENCT 3
|
||
|
#define VIU2_SEL_VENC_MASK 0xc
|
||
|
#define VIU2_SEL_VENC_ENCL 0
|
||
|
#define VIU2_SEL_VENC_ENCI (1 << 2)
|
||
|
#define VIU2_SEL_VENC_ENCP (2 << 2)
|
||
|
#define VIU2_SEL_VENC_ENCT (3 << 2)
|
||
|
#define VPU_HDMI_SETTING 0x271b
|
||
|
#define ENCI_INFO_READ 0x271c
|
||
|
#define ENCP_INFO_READ 0x271d
|
||
|
#define ENCT_INFO_READ 0x271e
|
||
|
#define ENCL_INFO_READ 0x271f
|
||
|
#define VPU_SW_RESET 0x2720
|
||
|
#define VPU_D2D3_MMC_CTRL 0x2721
|
||
|
#define VPU_CONT_MMC_CTRL 0x2722
|
||
|
#define VPU_CLK_GATE 0x2723
|
||
|
#define VPU_RDMA_MMC_CTRL 0x2724
|
||
|
#define VPU_MEM_PD_REG0 0x2725
|
||
|
#define VPU_MEM_PD_REG1 0x2726
|
||
|
#define VPU_HDMI_DATA_OVR 0x2727
|
||
|
#define VPU_PROT1_MMC_CTRL 0x2728
|
||
|
#define VPU_PROT2_MMC_CTRL 0x2729
|
||
|
#define VPU_PROT3_MMC_CTRL 0x272a
|
||
|
#define VPU_ARB4_V1_MMC_CTRL 0x272b
|
||
|
#define VPU_ARB4_V2_MMC_CTRL 0x272c
|
||
|
#define VPU_VPU_PWM_V0 0x2730
|
||
|
#define VPU_VPU_PWM_V1 0x2731
|
||
|
#define VPU_VPU_PWM_V2 0x2732
|
||
|
#define VPU_VPU_PWM_V3 0x2733
|
||
|
#define VPU_VPU_PWM_H0 0x2734
|
||
|
#define VPU_VPU_PWM_H1 0x2735
|
||
|
#define VPU_VPU_PWM_H2 0x2736
|
||
|
#define VPU_VPU_PWM_H3 0x2737
|
||
|
#define VPU_MISC_CTRL 0x2740
|
||
|
#define VPU_ISP_GCLK_CTRL0 0x2741
|
||
|
#define VPU_ISP_GCLK_CTRL1 0x2742
|
||
|
#define VPU_HDMI_FMT_CTRL 0x2743
|
||
|
#define VPU_VDIN_ASYNC_HOLD_CTRL 0x2743
|
||
|
#define VPU_VDISP_ASYNC_HOLD_CTRL 0x2744
|
||
|
#define VPU_VPUARB2_ASYNC_HOLD_CTRL 0x2745
|
||
|
|
||
|
#define VPU_PROT1_CLK_GATE 0x2750
|
||
|
#define VPU_PROT1_GEN_CNTL 0x2751
|
||
|
#define VPU_PROT1_X_START_END 0x2752
|
||
|
#define VPU_PROT1_Y_START_END 0x2753
|
||
|
#define VPU_PROT1_Y_LEN_STEP 0x2754
|
||
|
#define VPU_PROT1_RPT_LOOP 0x2755
|
||
|
#define VPU_PROT1_RPT_PAT 0x2756
|
||
|
#define VPU_PROT1_DDR 0x2757
|
||
|
#define VPU_PROT1_RBUF_ROOM 0x2758
|
||
|
#define VPU_PROT1_STAT_0 0x2759
|
||
|
#define VPU_PROT1_STAT_1 0x275a
|
||
|
#define VPU_PROT1_STAT_2 0x275b
|
||
|
#define VPU_PROT1_REQ_ONOFF 0x275c
|
||
|
#define VPU_PROT2_CLK_GATE 0x2760
|
||
|
#define VPU_PROT2_GEN_CNTL 0x2761
|
||
|
#define VPU_PROT2_X_START_END 0x2762
|
||
|
#define VPU_PROT2_Y_START_END 0x2763
|
||
|
#define VPU_PROT2_Y_LEN_STEP 0x2764
|
||
|
#define VPU_PROT2_RPT_LOOP 0x2765
|
||
|
#define VPU_PROT2_RPT_PAT 0x2766
|
||
|
#define VPU_PROT2_DDR 0x2767
|
||
|
#define VPU_PROT2_RBUF_ROOM 0x2768
|
||
|
#define VPU_PROT2_STAT_0 0x2769
|
||
|
#define VPU_PROT2_STAT_1 0x276a
|
||
|
#define VPU_PROT2_STAT_2 0x276b
|
||
|
#define VPU_PROT2_REQ_ONOFF 0x276c
|
||
|
#define VPU_PROT3_CLK_GATE 0x2770
|
||
|
#define VPU_PROT3_GEN_CNTL 0x2771
|
||
|
#define VPU_PROT3_X_START_END 0x2772
|
||
|
#define VPU_PROT3_Y_START_END 0x2773
|
||
|
#define VPU_PROT3_Y_LEN_STEP 0x2774
|
||
|
#define VPU_PROT3_RPT_LOOP 0x2775
|
||
|
#define VPU_PROT3_RPT_PAT 0x2776
|
||
|
#define VPU_PROT3_DDR 0x2777
|
||
|
#define VPU_PROT3_RBUF_ROOM 0x2778
|
||
|
#define VPU_PROT3_STAT_0 0x2779
|
||
|
#define VPU_PROT3_STAT_1 0x277a
|
||
|
#define VPU_PROT3_STAT_2 0x277b
|
||
|
#define VPU_PROT3_REQ_ONOFF 0x277c
|
||
|
#define VPU_RDARB_MODE_L1C1 0x2790
|
||
|
#define VPU_RDARB_MODE_L1C2 0x2799
|
||
|
#define VPU_RDARB_MODE_L2C1 0x279d
|
||
|
#define VPU_WRARB_MODE_L2C1 0x27a2
|
||
|
|
||
|
/* osd super scale */
|
||
|
#define OSDSR_HV_SIZEIN 0x3130
|
||
|
#define OSDSR_CTRL_MODE 0x3131
|
||
|
#define OSDSR_ABIC_HCOEF 0x3132
|
||
|
#define OSDSR_YBIC_HCOEF 0x3133
|
||
|
#define OSDSR_CBIC_HCOEF 0x3134
|
||
|
#define OSDSR_ABIC_VCOEF 0x3135
|
||
|
#define OSDSR_YBIC_VCOEF 0x3136
|
||
|
#define OSDSR_CBIC_VCOEF 0x3137
|
||
|
#define OSDSR_VAR_PARA 0x3138
|
||
|
#define OSDSR_CONST_PARA 0x3139
|
||
|
#define OSDSR_RKE_EXTWIN 0x313a
|
||
|
#define OSDSR_UK_GRAD2DDIAG_TH_RATE 0x313b
|
||
|
#define OSDSR_UK_GRAD2DDIAG_LIMIT 0x313c
|
||
|
#define OSDSR_UK_GRAD2DADJA_TH_RATE 0x313d
|
||
|
#define OSDSR_UK_GRAD2DADJA_LIMIT 0x313e
|
||
|
#define OSDSR_UK_BST_GAIN 0x313f
|
||
|
#define OSDSR_HVBLEND_TH 0x3140
|
||
|
#define OSDSR_DEMO_WIND_TB 0x3141
|
||
|
#define OSDSR_DEMO_WIND_LR 0x3142
|
||
|
#define OSDSR_INT_BLANK_NUM 0x3143
|
||
|
#define OSDSR_FRM_END_STAT 0x3144
|
||
|
#define OSDSR_ABIC_HCOEF0 0x3145
|
||
|
#define OSDSR_YBIC_HCOEF0 0x3146
|
||
|
#define OSDSR_CBIC_HCOEF0 0x3147
|
||
|
#define OSDSR_ABIC_VCOEF0 0x3148
|
||
|
#define OSDSR_YBIC_VCOEF0 0x3149
|
||
|
#define OSDSR_CBIC_VCOEF0 0x314a
|
||
|
|
||
|
#endif /* __MESON_REGISTERS_H */
|