2002-08-17 18:36:01 +09:00
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/*-----------------------------------------------------------------------------+
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1995
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+-----------------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------------+
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| File Name: miiphy.c
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| Function: This module has utilities for accessing the MII PHY through
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| the EMAC3 macro.
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| Author: Mark Wisner
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| Change Activity-
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| Date Description of Change BY
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| --------- --------------------- ---
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| 05-May-99 Created MKW
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| 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
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| better match OPB speed. Also modified delay times. JWB
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| 29-Jul-99 Added Full duplex support MKW
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| 24-Aug-99 Removed printf from dp83843_duplex() JWB
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| 19-Jul-00 Ported to esd cpci405 sr
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+-----------------------------------------------------------------------------*/
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#include <common.h>
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#include <asm/processor.h>
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#include <ppc_asm.tmpl>
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#include <commproc.h>
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#include <405gp_enet.h>
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#include <405_mal.h>
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#include <miiphy.h>
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2003-05-23 20:18:02 +09:00
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#if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
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2002-08-17 18:36:01 +09:00
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/***********************************************************/
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/* Dump out to the screen PHY regs */
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/***********************************************************/
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void miiphy_dump (unsigned char addr)
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{
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unsigned long i;
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unsigned short data;
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for (i = 0; i < 0x1A; i++) {
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if (miiphy_read (addr, i, &data)) {
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printf ("read error for reg %lx\n", i);
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return;
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}
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printf ("Phy reg %lx ==> %4x\n", i, data);
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/* jump to the next set of regs */
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if (i == 0x07)
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i = 0x0f;
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} /* end for loop */
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} /* end dump */
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/***********************************************************/
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/* read a phy reg and return the value with a rc */
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/***********************************************************/
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int miiphy_read (unsigned char addr, unsigned char reg,
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unsigned short *value)
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{
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unsigned long sta_reg; /* STA scratch area */
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unsigned long i;
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/* see if it is ready for 1000 nsec */
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i = 0;
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/* see if it is ready for sec */
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while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) {
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udelay (7);
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if (i > 5) {
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printf ("read err 1\n");
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return -1;
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}
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i++;
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}
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sta_reg = reg; /* reg address */
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/* set clock (50Mhz) and read flags */
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sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
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2003-09-03 07:48:03 +09:00
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sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
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2002-08-17 18:36:01 +09:00
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sta_reg = sta_reg | (addr << 5); /* Phy address */
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out32 (EMAC_STACR, sta_reg);
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#if 0 /* test-only */
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printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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#endif
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sta_reg = in32 (EMAC_STACR);
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i = 0;
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while ((sta_reg & EMAC_STACR_OC) == 0) {
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udelay (7);
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if (i > 5) {
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printf ("read err 2\n");
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return -1;
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}
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i++;
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sta_reg = in32 (EMAC_STACR);
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}
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if ((sta_reg & EMAC_STACR_PHYE) != 0) {
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printf ("read err 3\n");
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printf ("a2: read: EMAC_STACR=0x%0lx, i=%d\n",
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sta_reg, (int) i); /* test-only */
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return -1;
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}
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*value = *(short *) (&sta_reg);
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return 0;
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} /* phy_read */
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/***********************************************************/
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/* write a phy reg and return the value with a rc */
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/***********************************************************/
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int miiphy_write (unsigned char addr, unsigned char reg,
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unsigned short value)
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{
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unsigned long sta_reg; /* STA scratch area */
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unsigned long i;
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/* see if it is ready for 1000 nsec */
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i = 0;
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while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) {
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if (i > 5)
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return -1;
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udelay (7);
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i++;
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}
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sta_reg = 0;
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sta_reg = reg; /* reg address */
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/* set clock (50Mhz) and read flags */
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sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
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2003-09-03 07:48:03 +09:00
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sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
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2002-08-17 18:36:01 +09:00
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sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
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memcpy (&sta_reg, &value, 2); /* put in data */
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out32 (EMAC_STACR, sta_reg);
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/* wait for completion */
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i = 0;
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sta_reg = in32 (EMAC_STACR);
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while ((sta_reg & EMAC_STACR_OC) == 0) {
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udelay (7);
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if (i > 5)
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return -1;
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i++;
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sta_reg = in32 (EMAC_STACR);
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}
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if ((sta_reg & EMAC_STACR_PHYE) != 0)
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return -1;
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return 0;
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} /* phy_read */
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#endif /* CONFIG_405GP */
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