2016-06-03 22:11:36 +09:00
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1012ARDB_H__
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#define __LS1012ARDB_H__
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#include "ls1012a_common.h"
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2016-08-26 19:30:39 +09:00
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/* DDR */
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2016-06-03 22:11:36 +09:00
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#define CONFIG_NR_DRAM_BANKS 2
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000
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2016-08-26 19:30:39 +09:00
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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2016-06-03 22:11:36 +09:00
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#define CONFIG_CMD_MEMINFO
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#define CONFIG_CMD_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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2016-08-26 19:30:39 +09:00
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/* DDR board-specific timing parameters */
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#define CONFIG_MMDC_MDCTL 0x04180000
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#define CONFIG_MMDC_MDPDC 0x00030035
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#define CONFIG_MMDC_MDOTC 0x12554000
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#define CONFIG_MMDC_MDCFG0 0xbabf7954
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#define CONFIG_MMDC_MDCFG1 0xdb328f64
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#define CONFIG_MMDC_MDCFG2 0x01ff00db
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#define CONFIG_MMDC_MDMISC 0x00001680
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#define CONFIG_MMDC_MDREF 0x0f3c8000
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#define CONFIG_MMDC_MDRWD 0x00002000
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#define CONFIG_MMDC_MDOR 0x00bf1023
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#define CONFIG_MMDC_MDASP 0x0000003f
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#define CONFIG_MMDC_MPODTCTRL 0x0000022a
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#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003
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2016-06-03 22:11:36 +09:00
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/*
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* USB
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*/
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#define CONFIG_HAS_FSL_XHCI_USB
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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#define CONFIG_USB_XHCI_FSL
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#endif
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#define CONFIG_CMD_MEMINFO
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#define CONFIG_CMD_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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#endif /* __LS1012ARDB_H__ */
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