2011-01-20 16:49:52 +09:00
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/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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2012-08-17 19:43:48 +09:00
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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2011-01-20 16:49:52 +09:00
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#include <netdev.h>
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#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
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#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
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#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
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#define CLK_CODE_PATH(c) ((c) & 0xFF)
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#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
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#ifdef CONFIG_FSL_ESDHC
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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static int g_clk_mux_auto[8] = {
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CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
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CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
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};
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static int g_clk_mux_consumer[16] = {
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CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
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-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
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CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
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-1, -1, CLK_CODE(4, 2, 0), -1,
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};
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static int hsp_div_table[3][16] = {
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{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
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{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
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{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
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};
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u32 get_cpu_rev(void)
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{
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int reg;
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struct iim_regs *iim =
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(struct iim_regs *)IIM_BASE_ADDR;
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reg = readl(&iim->iim_srev);
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if (!reg) {
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reg = readw(ROMPATCH_REV);
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reg <<= 4;
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} else {
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reg += CHIP_REV_1_0;
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}
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return 0x35000 + (reg & 0xFF);
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}
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static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
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{
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int *pclk_mux;
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if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
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pclk_mux = g_clk_mux_consumer +
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((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
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MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
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} else {
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pclk_mux = g_clk_mux_auto +
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((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
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MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
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}
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if ((*pclk_mux) == -1)
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return -1;
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if (fi && fd) {
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if (!CLK_CODE_PATH(*pclk_mux)) {
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*fi = *fd = 1;
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return CLK_CODE_ARM(*pclk_mux);
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}
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if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
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*fi = 3;
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*fd = 4;
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} else {
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*fi = 2;
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*fd = 3;
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}
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}
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return CLK_CODE_ARM(*pclk_mux);
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}
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static int get_ahb_div(u32 pdr0)
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{
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int *pclk_mux;
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pclk_mux = g_clk_mux_consumer +
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((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
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MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
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if ((*pclk_mux) == -1)
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return -1;
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return CLK_CODE_AHB(*pclk_mux);
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}
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static u32 decode_pll(u32 reg, u32 infreq)
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{
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u32 mfi = (reg >> 10) & 0xf;
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u32 mfn = reg & 0x3f;
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u32 mfd = (reg >> 16) & 0x3f;
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u32 pd = (reg >> 26) & 0xf;
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mfi = mfi <= 5 ? 5 : mfi;
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mfd += 1;
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pd += 1;
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return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
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}
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static u32 get_mcu_main_clk(void)
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{
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u32 arm_div = 0, fi = 0, fd = 0;
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
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fi *=
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decode_pll(readl(&ccm->mpctl),
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CONFIG_MX35_HCLK_FREQ);
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return fi / (arm_div * fd);
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}
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static u32 get_ipg_clk(void)
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{
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u32 freq = get_mcu_main_clk();
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 pdr0 = readl(&ccm->pdr0);
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return freq / (get_ahb_div(pdr0) * 2);
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}
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static u32 get_ipg_per_clk(void)
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{
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u32 freq = get_mcu_main_clk();
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 pdr0 = readl(&ccm->pdr0);
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u32 pdr4 = readl(&ccm->pdr4);
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u32 div;
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if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
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div = (CCM_GET_DIVIDER(pdr4,
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MXC_CCM_PDR4_PER0_PRDF_MASK,
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MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
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(CCM_GET_DIVIDER(pdr4,
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MXC_CCM_PDR4_PER0_PODF_MASK,
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MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
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} else {
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div = CCM_GET_DIVIDER(pdr0,
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MXC_CCM_PDR0_PER_PODF_MASK,
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MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
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freq /= get_ahb_div(pdr0);
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}
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return freq / div;
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}
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u32 imx_get_uartclk(void)
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{
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u32 freq;
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 pdr4 = readl(&ccm->pdr4);
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if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
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freq = get_mcu_main_clk();
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} else {
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freq = decode_pll(readl(&ccm->ppctl),
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CONFIG_MX35_HCLK_FREQ);
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}
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freq /= ((CCM_GET_DIVIDER(pdr4,
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MXC_CCM_PDR4_UART_PRDF_MASK,
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MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
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(CCM_GET_DIVIDER(pdr4,
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MXC_CCM_PDR4_UART_PODF_MASK,
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MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
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return freq;
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}
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unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
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{
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u32 nfc_pdf, hsp_podf;
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u32 pll, ret_val = 0, usb_prdf, usb_podf;
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 reg = readl(&ccm->pdr0);
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u32 reg4 = readl(&ccm->pdr4);
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reg |= 0x1;
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switch (clk) {
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case CPU_CLK:
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ret_val = get_mcu_main_clk();
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break;
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case AHB_CLK:
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ret_val = get_mcu_main_clk();
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break;
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case HSP_CLK:
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if (reg & CLKMODE_CONSUMER) {
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hsp_podf = (reg >> 20) & 0x3;
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pll = get_mcu_main_clk();
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hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
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if (hsp_podf > 0) {
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ret_val = pll / hsp_podf;
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} else {
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puts("mismatch HSP with ARM clock setting\n");
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ret_val = 0;
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}
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} else {
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ret_val = get_mcu_main_clk();
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}
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break;
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case IPG_CLK:
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2011-10-13 14:34:59 +09:00
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ret_val = get_ipg_clk();
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2011-01-20 16:49:52 +09:00
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break;
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case IPG_PER_CLK:
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ret_val = get_ipg_per_clk();
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break;
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case NFC_CLK:
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nfc_pdf = (reg4 >> 28) & 0xF;
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pll = get_mcu_main_clk();
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/* AHB/nfc_pdf */
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ret_val = pll / (nfc_pdf + 1);
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break;
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case USB_CLK:
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usb_prdf = (reg4 >> 25) & 0x7;
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usb_podf = (reg4 >> 22) & 0x7;
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if (reg4 & 0x200) {
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pll = get_mcu_main_clk();
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} else {
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pll = decode_pll(readl(&ccm->ppctl),
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CONFIG_MX35_HCLK_FREQ);
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}
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ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
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break;
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default:
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printf("Unknown clock: %d\n", clk);
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break;
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}
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return ret_val;
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}
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unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk)
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{
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u32 ret_val = 0, pdf, pre_pdf, clk_sel;
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 mpdr2 = readl(&ccm->pdr2);
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u32 mpdr3 = readl(&ccm->pdr3);
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u32 mpdr4 = readl(&ccm->pdr4);
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switch (clk) {
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case UART1_BAUD:
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case UART2_BAUD:
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case UART3_BAUD:
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clk_sel = mpdr3 & (1 << 14);
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pre_pdf = (mpdr4 >> 13) & 0x7;
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pdf = (mpdr4 >> 10) & 0x7;
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case SSI1_BAUD:
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pre_pdf = (mpdr2 >> 24) & 0x7;
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pdf = mpdr2 & 0x3F;
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clk_sel = mpdr2 & (1 << 6);
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case SSI2_BAUD:
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pre_pdf = (mpdr2 >> 27) & 0x7;
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pdf = (mpdr2 >> 8) & 0x3F;
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clk_sel = mpdr2 & (1 << 6);
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case CSI_BAUD:
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clk_sel = mpdr2 & (1 << 7);
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pre_pdf = (mpdr2 >> 16) & 0x7;
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pdf = (mpdr2 >> 19) & 0x7;
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case MSHC_CLK:
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pre_pdf = readl(&ccm->pdr1);
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clk_sel = (pre_pdf & 0x80);
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pdf = (pre_pdf >> 22) & 0x3F;
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pre_pdf = (pre_pdf >> 28) & 0x7;
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case ESDHC1_CLK:
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clk_sel = mpdr3 & 0x40;
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pre_pdf = mpdr3 & 0x7;
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pdf = (mpdr3>>3) & 0x7;
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
|
|
|
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
|
|
|
((pre_pdf + 1) * (pdf + 1));
|
|
|
|
break;
|
|
|
|
case ESDHC2_CLK:
|
|
|
|
clk_sel = mpdr3 & 0x40;
|
|
|
|
pre_pdf = (mpdr3 >> 8) & 0x7;
|
|
|
|
pdf = (mpdr3 >> 11) & 0x7;
|
|
|
|
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
|
|
|
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
|
|
|
((pre_pdf + 1) * (pdf + 1));
|
|
|
|
break;
|
|
|
|
case ESDHC3_CLK:
|
|
|
|
clk_sel = mpdr3 & 0x40;
|
|
|
|
pre_pdf = (mpdr3 >> 16) & 0x7;
|
|
|
|
pdf = (mpdr3 >> 19) & 0x7;
|
|
|
|
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
|
|
|
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
|
|
|
((pre_pdf + 1) * (pdf + 1));
|
|
|
|
break;
|
|
|
|
case SPDIF_CLK:
|
|
|
|
clk_sel = mpdr3 & 0x400000;
|
|
|
|
pre_pdf = (mpdr3 >> 29) & 0x7;
|
|
|
|
pdf = (mpdr3 >> 23) & 0x3F;
|
|
|
|
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
|
|
|
|
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
|
|
|
|
((pre_pdf + 1) * (pdf + 1));
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("%s(): This clock: %d not supported yet\n",
|
|
|
|
__func__, clk);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret_val;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned int mxc_get_clock(enum mxc_clock clk)
|
|
|
|
{
|
|
|
|
switch (clk) {
|
|
|
|
case MXC_ARM_CLK:
|
|
|
|
return get_mcu_main_clk();
|
|
|
|
case MXC_AHB_CLK:
|
|
|
|
break;
|
|
|
|
case MXC_IPG_CLK:
|
|
|
|
return get_ipg_clk();
|
|
|
|
case MXC_IPG_PERCLK:
|
|
|
|
return get_ipg_per_clk();
|
|
|
|
case MXC_UART_CLK:
|
|
|
|
return imx_get_uartclk();
|
|
|
|
case MXC_ESDHC_CLK:
|
|
|
|
return mxc_get_peri_clock(ESDHC1_CLK);
|
|
|
|
case MXC_USB_CLK:
|
|
|
|
return mxc_get_main_clock(USB_CLK);
|
|
|
|
case MXC_FEC_CLK:
|
|
|
|
return get_ipg_clk();
|
|
|
|
case MXC_CSPI_CLK:
|
|
|
|
return get_ipg_clk();
|
|
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_FEC_MXC
|
|
|
|
/*
|
|
|
|
* The MX35 has no fuse for MAC, return a NULL MAC
|
|
|
|
*/
|
2011-12-20 14:46:31 +09:00
|
|
|
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
|
2011-01-20 16:49:52 +09:00
|
|
|
{
|
|
|
|
memset(mac, 0, 6);
|
|
|
|
}
|
|
|
|
|
|
|
|
u32 imx_get_fecclk(void)
|
|
|
|
{
|
|
|
|
return mxc_get_clock(MXC_IPG_CLK);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
int do_mx35_showclocks(cmd_tbl_t *cmdtp,
|
|
|
|
int flag, int argc, char * const argv[])
|
|
|
|
{
|
|
|
|
u32 cpufreq = get_mcu_main_clk();
|
|
|
|
printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
|
|
|
|
printf("ipg clock : %dHz\n", get_ipg_clk());
|
|
|
|
printf("ipg per clock : %dHz\n", get_ipg_per_clk());
|
|
|
|
printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
U_BOOT_CMD(
|
2011-08-18 00:52:40 +09:00
|
|
|
clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
|
|
|
|
"display clocks",
|
2011-01-20 16:49:52 +09:00
|
|
|
""
|
|
|
|
);
|
|
|
|
|
2012-02-10 14:34:03 +09:00
|
|
|
#if defined(CONFIG_DISPLAY_CPUINFO)
|
2011-08-05 19:21:37 +09:00
|
|
|
static char *get_reset_cause(void)
|
|
|
|
{
|
|
|
|
/* read RCSR register from CCM module */
|
|
|
|
struct ccm_regs *ccm =
|
|
|
|
(struct ccm_regs *)IMX_CCM_BASE;
|
|
|
|
|
|
|
|
u32 cause = readl(&ccm->rcsr) & 0x0F;
|
|
|
|
|
|
|
|
switch (cause) {
|
|
|
|
case 0x0000:
|
|
|
|
return "POR";
|
|
|
|
case 0x0002:
|
|
|
|
return "JTAG";
|
|
|
|
case 0x0004:
|
|
|
|
return "RST";
|
|
|
|
case 0x0008:
|
|
|
|
return "WDOG";
|
|
|
|
default:
|
|
|
|
return "unknown reset";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-01-20 16:49:52 +09:00
|
|
|
int print_cpuinfo(void)
|
|
|
|
{
|
2011-08-05 19:21:37 +09:00
|
|
|
u32 srev = get_cpu_rev();
|
|
|
|
|
|
|
|
printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
|
|
|
|
(srev & 0xF0) >> 4, (srev & 0x0F),
|
2011-01-20 16:49:52 +09:00
|
|
|
get_mcu_main_clk() / 1000000);
|
2011-08-05 19:21:37 +09:00
|
|
|
|
|
|
|
printf("Reset cause: %s\n", get_reset_cause());
|
|
|
|
|
2011-01-20 16:49:52 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initializes on-chip ethernet controllers.
|
|
|
|
* to override, implement board_eth_init()
|
|
|
|
*/
|
|
|
|
int cpu_eth_init(bd_t *bis)
|
|
|
|
{
|
|
|
|
int rc = -ENODEV;
|
|
|
|
|
|
|
|
#if defined(CONFIG_FEC_MXC)
|
|
|
|
rc = fecmxc_initialize(bis);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2012-08-17 19:43:48 +09:00
|
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
|
|
/*
|
|
|
|
* Initializes on-chip MMC controllers.
|
|
|
|
* to override, implement board_mmc_init()
|
|
|
|
*/
|
|
|
|
int cpu_mmc_init(bd_t *bis)
|
|
|
|
{
|
|
|
|
return fsl_esdhc_mmc_init(bis);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-01-20 16:49:52 +09:00
|
|
|
int get_clocks(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
|
|
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void reset_cpu(ulong addr)
|
|
|
|
{
|
|
|
|
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
|
|
|
|
writew(4, &wdog->wcr);
|
|
|
|
}
|