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https://github.com/brain-hackers/u-boot-brain
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382 lines
8.7 KiB
C
382 lines
8.7 KiB
C
![]() |
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2017-2019 NXP.
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*
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <linux/clk-provider.h>
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#include <linux/iopoll.h>
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#include <clk.h>
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#include <div64.h>
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#include "clk.h"
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#define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
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#define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
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#define GNRL_CTL 0x0
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#define DIV_CTL 0x4
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#define LOCK_STATUS BIT(31)
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#define LOCK_SEL_MASK BIT(29)
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#define CLKE_MASK BIT(11)
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#define RST_MASK BIT(9)
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#define BYPASS_MASK BIT(4)
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#define MDIV_SHIFT 12
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#define MDIV_MASK GENMASK(21, 12)
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#define PDIV_SHIFT 4
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#define PDIV_MASK GENMASK(9, 4)
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#define SDIV_SHIFT 0
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#define SDIV_MASK GENMASK(2, 0)
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#define KDIV_SHIFT 0
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#define KDIV_MASK GENMASK(15, 0)
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#define LOCK_TIMEOUT_US 10000
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struct clk_pll14xx {
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struct clk clk;
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void __iomem *base;
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enum imx_pll14xx_type type;
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const struct imx_pll14xx_rate_table *rate_table;
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int rate_count;
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};
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#define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
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static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
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struct clk_pll14xx *pll, unsigned long rate)
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{
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const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
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int i;
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for (i = 0; i < pll->rate_count; i++)
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if (rate == rate_table[i].rate)
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return &rate_table[i];
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return NULL;
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}
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static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
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{
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struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
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u64 fvco = clk_get_parent_rate(clk);
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u32 mdiv, pdiv, sdiv, pll_div;
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pll_div = readl(pll->base + 4);
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mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
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pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
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sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
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fvco *= mdiv;
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do_div(fvco, pdiv << sdiv);
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return fvco;
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}
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static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
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{
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struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
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u64 fvco = clk_get_parent_rate(clk);
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u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
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short int kdiv;
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pll_div_ctl0 = readl(pll->base + 4);
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pll_div_ctl1 = readl(pll->base + 8);
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mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
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pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
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sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
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kdiv = pll_div_ctl1 & KDIV_MASK;
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/* fvco = (m * 65536 + k) * Fin / (p * 65536) */
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fvco *= (mdiv * 65536 + kdiv);
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pdiv *= 65536;
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do_div(fvco, pdiv << sdiv);
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return fvco;
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}
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static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
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u32 pll_div)
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{
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u32 old_mdiv, old_pdiv;
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old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
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old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
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return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
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}
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static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
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u32 pll_div_ctl0, u32 pll_div_ctl1)
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{
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u32 old_mdiv, old_pdiv, old_kdiv;
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old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
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old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
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old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
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return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
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rate->kdiv != old_kdiv;
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}
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static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
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u32 pll_div_ctl0, u32 pll_div_ctl1)
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{
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u32 old_mdiv, old_pdiv, old_kdiv;
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old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
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old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
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old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
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return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
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rate->kdiv != old_kdiv;
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}
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static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
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{
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u32 val;
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return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
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LOCK_TIMEOUT_US);
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}
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static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
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{
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struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
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const struct imx_pll14xx_rate_table *rate;
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u32 tmp, div_val;
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int ret;
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rate = imx_get_pll_settings(pll, drate);
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if (!rate) {
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pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
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drate, "xxxx");
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return -EINVAL;
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}
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tmp = readl(pll->base + 4);
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if (!clk_pll1416x_mp_change(rate, tmp)) {
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tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
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tmp |= rate->sdiv << SDIV_SHIFT;
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writel(tmp, pll->base + 4);
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return clk_pll1416x_recalc_rate(clk);
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}
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/* Bypass clock and set lock to pll output lock */
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tmp = readl(pll->base);
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tmp |= LOCK_SEL_MASK;
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writel(tmp, pll->base);
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/* Enable RST */
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tmp &= ~RST_MASK;
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writel(tmp, pll->base);
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/* Enable BYPASS */
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tmp |= BYPASS_MASK;
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writel(tmp, pll->base);
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div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
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(rate->sdiv << SDIV_SHIFT);
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writel(div_val, pll->base + 0x4);
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/*
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* According to SPEC, t3 - t2 need to be greater than
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* 1us and 1/FREF, respectively.
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* FREF is FIN / Prediv, the prediv is [1, 63], so choose
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* 3us.
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*/
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udelay(3);
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/* Disable RST */
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tmp |= RST_MASK;
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writel(tmp, pll->base);
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/* Wait Lock */
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ret = clk_pll14xx_wait_lock(pll);
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if (ret)
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return ret;
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/* Bypass */
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tmp &= ~BYPASS_MASK;
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writel(tmp, pll->base);
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return clk_pll1416x_recalc_rate(clk);
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}
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static ulong clk_pll1443x_set_rate(struct clk *clk, unsigned long drate)
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{
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struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
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const struct imx_pll14xx_rate_table *rate;
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u32 tmp, div_val;
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int ret;
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rate = imx_get_pll_settings(pll, drate);
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if (!rate) {
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pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
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drate, "===");
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return -EINVAL;
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}
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tmp = readl(pll->base + 4);
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div_val = readl(pll->base + 8);
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if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
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tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
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tmp |= rate->sdiv << SDIV_SHIFT;
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writel(tmp, pll->base + 4);
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return clk_pll1443x_recalc_rate(clk);
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}
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tmp = readl(pll->base);
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/* Enable RST */
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tmp &= ~RST_MASK;
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writel(tmp, pll->base);
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/* Enable BYPASS */
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tmp |= BYPASS_MASK;
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writel(tmp, pll->base);
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div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
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(rate->sdiv << SDIV_SHIFT);
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writel(div_val, pll->base + 0x4);
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writel(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
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/*
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* According to SPEC, t3 - t2 need to be greater than
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* 1us and 1/FREF, respectively.
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* FREF is FIN / Prediv, the prediv is [1, 63], so choose
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* 3us.
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*/
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udelay(3);
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/* Disable RST */
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tmp |= RST_MASK;
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writel(tmp, pll->base);
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/* Wait Lock*/
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ret = clk_pll14xx_wait_lock(pll);
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if (ret)
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return ret;
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/* Bypass */
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tmp &= ~BYPASS_MASK;
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writel(tmp, pll->base);
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return clk_pll1443x_recalc_rate(clk);
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}
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static int clk_pll14xx_prepare(struct clk *clk)
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{
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struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
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u32 val;
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/*
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* RESETB = 1 from 0, PLL starts its normal
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* operation after lock time
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*/
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val = readl(pll->base + GNRL_CTL);
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val |= RST_MASK;
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writel(val, pll->base + GNRL_CTL);
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return clk_pll14xx_wait_lock(pll);
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}
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static int clk_pll14xx_unprepare(struct clk *clk)
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{
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struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
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u32 val;
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/*
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* Set RST to 0, power down mode is enabled and
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* every digital block is reset
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*/
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val = readl(pll->base + GNRL_CTL);
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val &= ~RST_MASK;
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writel(val, pll->base + GNRL_CTL);
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return 0;
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}
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static const struct clk_ops clk_pll1416x_ops = {
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.enable = clk_pll14xx_prepare,
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.disable = clk_pll14xx_unprepare,
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.set_rate = clk_pll1416x_set_rate,
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.get_rate = clk_pll1416x_recalc_rate,
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};
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static const struct clk_ops clk_pll1443x_ops = {
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.enable = clk_pll14xx_prepare,
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.disable = clk_pll14xx_unprepare,
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.set_rate = clk_pll1443x_set_rate,
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.get_rate = clk_pll1443x_recalc_rate,
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};
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struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
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void __iomem *base,
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const struct imx_pll14xx_clk *pll_clk)
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{
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struct clk_pll14xx *pll;
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struct clk *clk;
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char *type_name;
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int ret;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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switch (pll_clk->type) {
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case PLL_1416X:
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type_name = UBOOT_DM_CLK_IMX_PLL1416X;
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break;
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case PLL_1443X:
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type_name = UBOOT_DM_CLK_IMX_PLL1443X;
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break;
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default:
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pr_err("%s: Unknown pll type for pll clk %s\n",
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__func__, name);
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return ERR_PTR(-EINVAL);
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};
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pll->base = base;
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pll->type = pll_clk->type;
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pll->rate_table = pll_clk->rate_table;
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pll->rate_count = pll_clk->rate_count;
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clk = &pll->clk;
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ret = clk_register(clk, type_name, name, parent_name);
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if (ret) {
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pr_err("%s: failed to register pll %s %d\n",
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__func__, name, ret);
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kfree(pll);
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return ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(clk_pll1443x) = {
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.name = UBOOT_DM_CLK_IMX_PLL1443X,
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.id = UCLASS_CLK,
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.ops = &clk_pll1443x_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DRIVER(clk_pll1416x) = {
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.name = UBOOT_DM_CLK_IMX_PLL1416X,
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.id = UCLASS_CLK,
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.ops = &clk_pll1416x_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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