mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
197 lines
6.1 KiB
C
197 lines
6.1 KiB
C
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/*
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* (C) Copyright 2000
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Code in faintly related to linux/arch/ppc/8xx_io:
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* MPC8xx CPM I2C interface. Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
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*
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* This file implements functions to read the MBX's Vital Product Data
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* (VPD). I can't use the more general i2c code in mpc8xx/... since I need
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* the VPD at a time where there is no RAM available yet. Hence the VPD is
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* read into a special area in the DPRAM (see config_MBX.h::CFG_DPRAMVPD).
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*
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* -----------------------------------------------------------------
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CONFIG_8xx
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#include <commproc.h>
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#endif
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#include "vpd.h"
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/* Location of receive/transmit buffer descriptors
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* Allocate one transmit bd and one receive bd.
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* IIC_BD_FREE points to free bd space which we'll use as tx buffer.
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*/
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#define IIC_BD_TX1 (BD_IIC_START + 0*sizeof(cbd_t))
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#define IIC_BD_TX2 (BD_IIC_START + 1*sizeof(cbd_t))
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#define IIC_BD_RX (BD_IIC_START + 2*sizeof(cbd_t))
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#define IIC_BD_FREE (BD_IIC_START + 3*sizeof(cbd_t))
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/* FIXME -- replace 0x2000 with offsetof */
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#define VPD_P ((vpd_t *)(CFG_IMMR + 0x2000 + CFG_DPRAMVPD))
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/* transmit/receive buffers */
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#define IIC_RX_LENGTH 128
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#define WITH_MICROCODE_PATCH
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vpd_packet_t * vpd_find_packet(u_char ident)
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{
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vpd_packet_t *packet;
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vpd_t *vpd = VPD_P;
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packet = (vpd_packet_t *)&vpd->packets;
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while ((packet->identifier != ident) && packet->identifier != 0xFF)
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{
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packet = (vpd_packet_t *)((char *)packet + packet->size + 2);
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}
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return packet;
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}
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void vpd_init(void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c);
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volatile iic_t *iip;
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#ifdef WITH_MICROCODE_PATCH
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ulong reloc = 0;
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#endif
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iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
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/*
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* kludge: when running from flash, no microcode patch can be
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* installed. However, the DPMEM usually contains non-zero
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* garbage at the relocatable patch base location, so lets clear
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* it now. This way the rest of the code can support the microcode
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* patch dynamically.
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*/
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if ((ulong)vpd_init & 0xff000000)
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iip->iic_rpbase = 0;
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#ifdef WITH_MICROCODE_PATCH
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/* Check for and use a microcode relocation patch. */
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if ((reloc = iip->iic_rpbase))
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iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
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#endif
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/* Initialize Port B IIC pins */
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cp->cp_pbpar |= 0x00000030;
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cp->cp_pbdir |= 0x00000030;
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cp->cp_pbodr |= 0x00000030;
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i2c->i2c_i2mod = 0x04; /* filter clock */
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i2c->i2c_i2add = 0x34; /* select an arbitrary (unique) address */
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i2c->i2c_i2brg = 0x07; /* make clock run maximum slow */
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i2c->i2c_i2cmr = 0x00; /* disable interrupts */
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i2c->i2c_i2cer = 0x1f; /* clear events */
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i2c->i2c_i2com = 0x01; /* configure i2c to work as master */
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if (vpd_read(0xa4, (uchar*)VPD_P, VPD_EEPROM_SIZE, 0) != VPD_EEPROM_SIZE)
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{
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hang();
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}
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}
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/* Read from I2C.
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* This is a two step process. First, we send the "dummy" write
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* to set the device offset for the read. Second, we perform
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* the read operation.
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*/
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int vpd_read(uint iic_device, uchar *buf, int count, int offset)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c);
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volatile iic_t *iip;
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volatile cbd_t *tbdf1, *tbdf2, *rbdf;
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uchar *tb;
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uchar event;
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#ifdef WITH_MICROCODE_PATCH
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ulong reloc = 0;
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#endif
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iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
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#ifdef WITH_MICROCODE_PATCH
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/* Check for and use a microcode relocation patch. */
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if ((reloc = iip->iic_rpbase))
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iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
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#endif
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tbdf1 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX1];
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tbdf2 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX2];
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rbdf = (cbd_t *)&cp->cp_dpmem[IIC_BD_RX];
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/* Send a "dummy write" operation. This is a write request with
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* only the offset sent, followed by another start condition.
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* This will ensure we start reading from the first location
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* of the EEPROM.
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*/
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tb = (uchar*)&cp->cp_dpmem[IIC_BD_FREE];
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tb[0] = iic_device & 0xfe; /* device address */
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tb[1] = offset; /* offset */
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tbdf1->cbd_bufaddr = (uint)tb;
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tbdf1->cbd_datlen = 2;
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tbdf1->cbd_sc = 0x8400;
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tb += 2;
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tb[0] = iic_device | 1; /* device address */
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tbdf2->cbd_bufaddr = (uint)tb;
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tbdf2->cbd_datlen = count+1;
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tbdf2->cbd_sc = 0xbc00;
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rbdf->cbd_bufaddr = (uint)buf;
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rbdf->cbd_datlen = 0;
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rbdf->cbd_sc = 0xb000;
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iip->iic_tbase = IIC_BD_TX1;
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iip->iic_tbptr = IIC_BD_TX1;
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iip->iic_rbase = IIC_BD_RX;
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iip->iic_rbptr = IIC_BD_RX;
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iip->iic_rfcr = 0x15;
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iip->iic_tfcr = 0x15;
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iip->iic_mrblr = count;
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iip->iic_rstate = 0;
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iip->iic_tstate = 0;
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i2c->i2c_i2cer = 0x1f; /* clear event mask */
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i2c->i2c_i2mod |= 1; /* enable iic operation */
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i2c->i2c_i2com |= 0x80; /* start master */
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/* wait for IIC transfer */
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do {
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__asm__ volatile ("eieio");
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event = i2c->i2c_i2cer;
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} while (event == 0);
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if ((event & 0x10) || (event & 0x04)) {
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count = -1;
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goto bailout;
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}
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bailout:
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i2c->i2c_i2mod &= ~1; /* turn off iic operation */
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i2c->i2c_i2cer = 0x1f; /* clear event mask */
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return count;
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}
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