2008-10-31 06:47:16 +09:00
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/*
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2011-01-07 14:42:19 +09:00
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* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
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2008-10-31 06:47:16 +09:00
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* Andy Fleming
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*
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* Based vaguely on the pxa mmc code:
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* (C) Copyright 2003
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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2013-07-08 16:37:19 +09:00
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* SPDX-License-Identifier: GPL-2.0+
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2008-10-31 06:47:16 +09:00
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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2016-07-19 16:33:36 +09:00
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#include <errno.h>
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2009-06-10 05:25:29 +09:00
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#include <hwconfig.h>
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2008-10-31 06:47:16 +09:00
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#include <mmc.h>
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#include <part.h>
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2017-06-12 18:50:54 +09:00
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#include <power/regulator.h>
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2008-10-31 06:47:16 +09:00
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#include <malloc.h>
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#include <fsl_esdhc.h>
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2009-06-10 05:25:29 +09:00
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#include <fdt_support.h>
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2008-10-31 06:47:16 +09:00
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#include <asm/io.h>
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2016-03-25 15:16:56 +09:00
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#include <dm.h>
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#include <asm-generic/gpio.h>
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2008-10-31 06:47:16 +09:00
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DECLARE_GLOBAL_DATA_PTR;
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2014-11-04 16:35:49 +09:00
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#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
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IRQSTATEN_CINT | \
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IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
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IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
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IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
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IRQSTATEN_DINT)
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2008-10-31 06:47:16 +09:00
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struct fsl_esdhc {
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2013-10-30 12:37:55 +09:00
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uint dsaddr; /* SDMA system address register */
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uint blkattr; /* Block attributes register */
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uint cmdarg; /* Command argument register */
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uint xfertyp; /* Transfer type register */
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uint cmdrsp0; /* Command response 0 register */
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uint cmdrsp1; /* Command response 1 register */
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uint cmdrsp2; /* Command response 2 register */
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uint cmdrsp3; /* Command response 3 register */
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uint datport; /* Buffer data port register */
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uint prsstat; /* Present state register */
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uint proctl; /* Protocol control register */
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uint sysctl; /* System Control Register */
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uint irqstat; /* Interrupt status register */
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uint irqstaten; /* Interrupt status enable register */
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uint irqsigen; /* Interrupt signal enable register */
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uint autoc12err; /* Auto CMD error status register */
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uint hostcapblt; /* Host controller capabilities register */
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uint wml; /* Watermark level register */
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uint mixctrl; /* For USDHC */
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char reserved1[4]; /* reserved */
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uint fevt; /* Force event register */
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uint admaes; /* ADMA error status register */
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uint adsaddr; /* ADMA system address register */
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2016-06-15 11:53:00 +09:00
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char reserved2[4];
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uint dllctrl;
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uint dllstat;
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uint clktunectrlstatus;
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char reserved3[84];
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uint vendorspec;
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uint mmcboot;
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uint vendorspec2;
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char reserved4[48];
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2013-10-30 12:37:55 +09:00
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uint hostver; /* Host controller version register */
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char reserved5[4]; /* reserved */
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2016-06-15 11:53:00 +09:00
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uint dmaerraddr; /* DMA error address register */
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2015-02-17 21:42:43 +09:00
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char reserved6[4]; /* reserved */
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2016-06-15 11:53:00 +09:00
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uint dmaerrattr; /* DMA error attribute register */
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char reserved7[4]; /* reserved */
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2013-10-30 12:37:55 +09:00
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uint hostcapblt2; /* Host controller capabilities register 2 */
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2016-06-15 11:53:00 +09:00
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char reserved8[8]; /* reserved */
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2013-10-30 12:37:55 +09:00
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uint tcr; /* Tuning control register */
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2016-06-15 11:53:00 +09:00
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char reserved9[28]; /* reserved */
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2013-10-30 12:37:55 +09:00
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uint sddirctl; /* SD direction control register */
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2016-06-15 11:53:00 +09:00
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char reserved10[712];/* reserved */
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2013-10-30 12:37:55 +09:00
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uint scr; /* eSDHC control register */
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2008-10-31 06:47:16 +09:00
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};
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2017-07-30 02:35:21 +09:00
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struct fsl_esdhc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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2016-03-25 15:16:56 +09:00
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/**
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* struct fsl_esdhc_priv
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*
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* @esdhc_regs: registers of the sdhc controller
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* @sdhc_clk: Current clk of the sdhc controller
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* @bus_width: bus width, 1bit, 4bit or 8bit
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* @cfg: mmc config
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* @mmc: mmc
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* Following is used when Driver Model is enabled for MMC
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* @dev: pointer for the device
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* @non_removable: 0: removable; 1: non-removable
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mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-15 11:53:02 +09:00
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* @wp_enable: 1: enable checking wp; 0: no check
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2017-06-12 18:50:53 +09:00
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* @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
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2016-03-25 15:16:56 +09:00
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* @cd_gpio: gpio for card detection
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mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-15 11:53:02 +09:00
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* @wp_gpio: gpio for write protection
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2016-03-25 15:16:56 +09:00
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*/
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struct fsl_esdhc_priv {
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struct fsl_esdhc *esdhc_regs;
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unsigned int sdhc_clk;
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unsigned int bus_width;
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2017-07-30 02:35:24 +09:00
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#if !CONFIG_IS_ENABLED(BLK)
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2016-03-25 15:16:56 +09:00
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struct mmc *mmc;
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2017-07-30 02:35:24 +09:00
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#endif
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2016-03-25 15:16:56 +09:00
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struct udevice *dev;
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int non_removable;
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mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-15 11:53:02 +09:00
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int wp_enable;
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2017-06-12 18:50:53 +09:00
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int vs18_enable;
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2016-12-07 12:54:30 +09:00
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#ifdef CONFIG_DM_GPIO
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2016-03-25 15:16:56 +09:00
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struct gpio_desc cd_gpio;
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mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-15 11:53:02 +09:00
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struct gpio_desc wp_gpio;
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2016-12-07 12:54:30 +09:00
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#endif
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2016-03-25 15:16:56 +09:00
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};
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2008-10-31 06:47:16 +09:00
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/* Return the XFERTYP flags for a given command and data packet */
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2012-10-29 22:34:44 +09:00
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static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
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2008-10-31 06:47:16 +09:00
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{
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uint xfertyp = 0;
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if (data) {
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2009-10-05 19:11:58 +09:00
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xfertyp |= XFERTYP_DPSEL;
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#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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xfertyp |= XFERTYP_DMAEN;
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#endif
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2008-10-31 06:47:16 +09:00
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if (data->blocks > 1) {
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xfertyp |= XFERTYP_MSBSEL;
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xfertyp |= XFERTYP_BCEN;
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2011-01-07 14:42:19 +09:00
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
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xfertyp |= XFERTYP_AC12EN;
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#endif
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2008-10-31 06:47:16 +09:00
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}
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if (data->flags & MMC_DATA_READ)
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xfertyp |= XFERTYP_DTDSEL;
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}
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if (cmd->resp_type & MMC_RSP_CRC)
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xfertyp |= XFERTYP_CCCEN;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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xfertyp |= XFERTYP_CICEN;
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if (cmd->resp_type & MMC_RSP_136)
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xfertyp |= XFERTYP_RSPTYP_136;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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xfertyp |= XFERTYP_RSPTYP_48_BUSY;
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else if (cmd->resp_type & MMC_RSP_PRESENT)
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xfertyp |= XFERTYP_RSPTYP_48;
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fsl_esdhc: Fix multi-block read restriction on i.MX53 eSDHCv2
For freescale i.MX53 eSDHCv2, when using CMD12, cmdtype need
to be set to ABORT, otherwise, next read command will hang.
This is a software Software Restrictions in i.MX53 reference manual:
29.7.8 Multi-block Read
For pre-defined multi-block read operation, that is,the number of blocks
to read has been defined by previous CMD23 for MMC, or pre-defined number
of blocks in CMD53 for SDIO/SDCombo,or whatever multi-block read without
abort command at card side, an abort command, either automatic or manual
CMD12/CMD52, is still required by ESDHC after the pre-defined number of
blocks are done, to drive the internal state machine to idle mode. In this
case, the card may not respond to this extra abort command and ESDHC will
get Response Timeout. It is recommended to manually send an abort command
with RSPTYP[1:0] both bits cleared.
Signed-off-by: Jason Liu <jason.hui@linaro.org>
2011-03-22 10:32:31 +09:00
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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xfertyp |= XFERTYP_CMDTYP_ABORT;
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2016-01-21 18:33:19 +09:00
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2008-10-31 06:47:16 +09:00
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return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
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}
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2009-10-05 19:11:58 +09:00
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#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
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/*
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* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
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*/
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2017-07-30 02:35:17 +09:00
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static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
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struct mmc_data *data)
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2009-10-05 19:11:58 +09:00
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{
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2016-03-25 15:16:56 +09:00
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struct fsl_esdhc *regs = priv->esdhc_regs;
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2009-10-05 19:11:58 +09:00
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uint blocks;
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char *buffer;
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uint databuf;
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uint size;
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uint irqstat;
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2017-10-30 06:08:58 +09:00
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ulong start;
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2009-10-05 19:11:58 +09:00
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if (data->flags & MMC_DATA_READ) {
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blocks = data->blocks;
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buffer = data->dest;
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while (blocks) {
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2017-10-30 06:08:58 +09:00
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start = get_timer(0);
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2009-10-05 19:11:58 +09:00
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size = data->blocksize;
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irqstat = esdhc_read32(®s->irqstat);
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2017-10-30 06:08:58 +09:00
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while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
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if (get_timer(start) > PIO_TIMEOUT) {
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printf("\nData Read Failed in PIO Mode.");
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return;
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}
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2009-10-05 19:11:58 +09:00
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}
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while (size && (!(irqstat & IRQSTAT_TC))) {
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udelay(100); /* Wait before last byte transfer complete */
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irqstat = esdhc_read32(®s->irqstat);
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databuf = in_le32(®s->datport);
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*((uint *)buffer) = databuf;
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buffer += 4;
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size -= 4;
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}
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blocks--;
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}
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} else {
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blocks = data->blocks;
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2010-05-10 06:52:59 +09:00
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buffer = (char *)data->src;
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2009-10-05 19:11:58 +09:00
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while (blocks) {
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2017-10-30 06:08:58 +09:00
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start = get_timer(0);
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2009-10-05 19:11:58 +09:00
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size = data->blocksize;
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irqstat = esdhc_read32(®s->irqstat);
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2017-10-30 06:08:58 +09:00
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while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
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if (get_timer(start) > PIO_TIMEOUT) {
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printf("\nData Write Failed in PIO Mode.");
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return;
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}
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2009-10-05 19:11:58 +09:00
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}
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while (size && (!(irqstat & IRQSTAT_TC))) {
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udelay(100); /* Wait before last byte transfer complete */
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databuf = *((uint *)buffer);
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buffer += 4;
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size -= 4;
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irqstat = esdhc_read32(®s->irqstat);
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out_le32(®s->datport, databuf);
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}
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blocks--;
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}
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}
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}
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#endif
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2017-07-30 02:35:17 +09:00
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static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
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struct mmc_data *data)
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2008-10-31 06:47:16 +09:00
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{
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int timeout;
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2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2016-06-05 09:43:00 +09:00
|
|
|
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
|
2015-03-21 11:28:31 +09:00
|
|
|
dma_addr_t addr;
|
|
|
|
#endif
|
2010-05-10 06:52:59 +09:00
|
|
|
uint wml_value;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
wml_value = data->blocksize/4;
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ) {
|
2011-02-09 12:54:10 +09:00
|
|
|
if (wml_value > WML_RD_WML_MAX)
|
|
|
|
wml_value = WML_RD_WML_MAX_VAL;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2010-02-09 19:23:33 +09:00
|
|
|
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
|
2014-02-20 19:00:57 +09:00
|
|
|
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
|
2016-06-05 09:43:00 +09:00
|
|
|
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
|
2015-03-21 11:28:31 +09:00
|
|
|
addr = virt_to_phys((void *)(data->dest));
|
|
|
|
if (upper_32_bits(addr))
|
|
|
|
printf("Error found for upper 32 bits\n");
|
|
|
|
else
|
|
|
|
esdhc_write32(®s->dsaddr, lower_32_bits(addr));
|
|
|
|
#else
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->dsaddr, (u32)data->dest);
|
2015-03-21 11:28:31 +09:00
|
|
|
#endif
|
2014-02-20 19:00:57 +09:00
|
|
|
#endif
|
2008-10-31 06:47:16 +09:00
|
|
|
} else {
|
2014-02-20 19:00:57 +09:00
|
|
|
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
|
2012-04-25 23:28:48 +09:00
|
|
|
flush_dcache_range((ulong)data->src,
|
|
|
|
(ulong)data->src+data->blocks
|
|
|
|
*data->blocksize);
|
2014-02-20 19:00:57 +09:00
|
|
|
#endif
|
2011-02-09 12:54:10 +09:00
|
|
|
if (wml_value > WML_WR_WML_MAX)
|
|
|
|
wml_value = WML_WR_WML_MAX_VAL;
|
mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-15 11:53:02 +09:00
|
|
|
if (priv->wp_enable) {
|
|
|
|
if ((esdhc_read32(®s->prsstat) &
|
|
|
|
PRSSTAT_WPSPL) == 0) {
|
|
|
|
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
|
2016-07-19 16:33:36 +09:00
|
|
|
return -ETIMEDOUT;
|
mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-15 11:53:02 +09:00
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
2010-02-09 19:23:33 +09:00
|
|
|
|
|
|
|
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
|
|
|
|
wml_value << 16);
|
2014-02-20 19:00:57 +09:00
|
|
|
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
|
2016-06-05 09:43:00 +09:00
|
|
|
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
|
2015-03-21 11:28:31 +09:00
|
|
|
addr = virt_to_phys((void *)(data->src));
|
|
|
|
if (upper_32_bits(addr))
|
|
|
|
printf("Error found for upper 32 bits\n");
|
|
|
|
else
|
|
|
|
esdhc_write32(®s->dsaddr, lower_32_bits(addr));
|
|
|
|
#else
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->dsaddr, (u32)data->src);
|
2015-03-21 11:28:31 +09:00
|
|
|
#endif
|
2014-02-20 19:00:57 +09:00
|
|
|
#endif
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Calculate the timeout period for data transactions */
|
2011-03-03 12:48:56 +09:00
|
|
|
/*
|
|
|
|
* 1)Timeout period = (2^(timeout+13)) SD Clock cycles
|
|
|
|
* 2)Timeout period should be minimum 0.250sec as per SD Card spec
|
|
|
|
* So, Number of SD Clock cycles for 0.25sec should be minimum
|
|
|
|
* (SD Clock/sec * 0.25 sec) SD Clock cycles
|
mmc: fsl_esdhc: fix calculation of timeout for data transactions
Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 16:40:41 +09:00
|
|
|
* = (mmc->clock * 1/4) SD Clock cycles
|
2011-03-03 12:48:56 +09:00
|
|
|
* As 1) >= 2)
|
mmc: fsl_esdhc: fix calculation of timeout for data transactions
Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 16:40:41 +09:00
|
|
|
* => (2^(timeout+13)) >= mmc->clock * 1/4
|
2011-03-03 12:48:56 +09:00
|
|
|
* Taking log2 both the sides
|
mmc: fsl_esdhc: fix calculation of timeout for data transactions
Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 16:40:41 +09:00
|
|
|
* => timeout + 13 >= log2(mmc->clock/4)
|
2011-03-03 12:48:56 +09:00
|
|
|
* Rounding up to next power of 2
|
mmc: fsl_esdhc: fix calculation of timeout for data transactions
Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 16:40:41 +09:00
|
|
|
* => timeout + 13 = log2(mmc->clock/4) + 1
|
|
|
|
* => timeout + 13 = fls(mmc->clock/4)
|
2015-12-30 15:19:30 +09:00
|
|
|
*
|
|
|
|
* However, the MMC spec "It is strongly recommended for hosts to
|
|
|
|
* implement more than 500ms timeout value even if the card
|
|
|
|
* indicates the 250ms maximum busy length." Even the previous
|
|
|
|
* value of 300ms is known to be insufficient for some cards.
|
|
|
|
* So, we use
|
|
|
|
* => timeout + 13 = fls(mmc->clock/2)
|
2011-03-03 12:48:56 +09:00
|
|
|
*/
|
2015-12-30 15:19:30 +09:00
|
|
|
timeout = fls(mmc->clock/2);
|
2008-10-31 06:47:16 +09:00
|
|
|
timeout -= 13;
|
|
|
|
|
|
|
|
if (timeout > 14)
|
|
|
|
timeout = 14;
|
|
|
|
|
|
|
|
if (timeout < 0)
|
|
|
|
timeout = 0;
|
|
|
|
|
2011-01-30 06:36:10 +09:00
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
|
|
|
|
if ((timeout == 4) || (timeout == 8) || (timeout == 12))
|
|
|
|
timeout++;
|
|
|
|
#endif
|
|
|
|
|
2014-03-18 18:04:23 +09:00
|
|
|
#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
|
|
|
|
timeout = 0xE;
|
|
|
|
#endif
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-04-25 23:28:48 +09:00
|
|
|
static void check_and_invalidate_dcache_range
|
|
|
|
(struct mmc_cmd *cmd,
|
|
|
|
struct mmc_data *data) {
|
2015-03-21 11:28:31 +09:00
|
|
|
unsigned start = 0;
|
2016-05-12 20:12:58 +09:00
|
|
|
unsigned end = 0;
|
2012-04-25 23:28:48 +09:00
|
|
|
unsigned size = roundup(ARCH_DMA_MINALIGN,
|
|
|
|
data->blocks*data->blocksize);
|
2016-06-05 09:43:00 +09:00
|
|
|
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
|
2015-03-21 11:28:31 +09:00
|
|
|
dma_addr_t addr;
|
|
|
|
|
|
|
|
addr = virt_to_phys((void *)(data->dest));
|
|
|
|
if (upper_32_bits(addr))
|
|
|
|
printf("Error found for upper 32 bits\n");
|
|
|
|
else
|
|
|
|
start = lower_32_bits(addr);
|
2016-05-12 20:12:58 +09:00
|
|
|
#else
|
|
|
|
start = (unsigned)data->dest;
|
2015-03-21 11:28:31 +09:00
|
|
|
#endif
|
2016-05-12 20:12:58 +09:00
|
|
|
end = start + size;
|
2012-04-25 23:28:48 +09:00
|
|
|
invalidate_dcache_range(start, end);
|
|
|
|
}
|
2014-05-23 22:19:05 +09:00
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
/*
|
|
|
|
* Sends a command out on the bus. Takes the mmc pointer,
|
|
|
|
* a command pointer, and an optional data pointer.
|
|
|
|
*/
|
2017-07-30 02:35:18 +09:00
|
|
|
static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|
|
|
struct mmc_cmd *cmd, struct mmc_data *data)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
2014-03-24 16:41:06 +09:00
|
|
|
int err = 0;
|
2008-10-31 06:47:16 +09:00
|
|
|
uint xfertyp;
|
|
|
|
uint irqstat;
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2011-01-07 14:42:19 +09:00
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
|
|
|
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->irqstat, -1);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
sync();
|
|
|
|
|
|
|
|
/* Wait for the bus to be idle */
|
2010-02-05 23:11:27 +09:00
|
|
|
while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
|
|
|
|
(esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
|
|
|
|
;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
|
|
|
|
;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Wait at least 8 SD clock cycles before the next command */
|
|
|
|
/*
|
|
|
|
* Note: This is way more than 8 cycles, but 1ms seems to
|
|
|
|
* resolve timing issues with some cards
|
|
|
|
*/
|
|
|
|
udelay(1000);
|
|
|
|
|
|
|
|
/* Set up for a data transfer if we have one */
|
|
|
|
if (data) {
|
2017-07-30 02:35:17 +09:00
|
|
|
err = esdhc_setup_data(priv, mmc, data);
|
2008-10-31 06:47:16 +09:00
|
|
|
if(err)
|
|
|
|
return err;
|
2015-06-25 11:32:26 +09:00
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ)
|
|
|
|
check_and_invalidate_dcache_range(cmd, data);
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Figure out the transfer arguments */
|
|
|
|
xfertyp = esdhc_xfertyp(cmd, data);
|
|
|
|
|
fsl_esdhc: Do not clear interrupt status bits until data processed
After waiting for the command completion event, the interrupt status
bits, that occured to be set by that time, are cleared by writing them
back. It is supposed, that it should be command related bits (command
complete and may be command errors).
However, in some cases the DMA already completes by that time before
the full transaction completes. The corresponding DINT bit gets set
and then cleared before even entering the loop, waiting for data part
completion. That waiting loop never gets this bit set, causing the
operation to hang. This is reported to happen, for example, for write
operation of 1 sector to upper area (block #7400000) of SanDisk Ultra II
8GB card.
The solution could be to explicitly clear only command related interrupt
status bits. However, since subsequent processing does not rely on
any command bits state, it could be easier just to remove clearing
of any bits at that point, leaving them all until all data processing
completes. After that the whole register will be cleared at once.
Also, on occasion, interrupts masking moved to before writing the command,
just for the case there should be no chance of interrupt between the first
command and interrupts masking.
Reported-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-12 00:34:22 +09:00
|
|
|
/* Mask all irqs */
|
|
|
|
esdhc_write32(®s->irqsigen, 0);
|
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
/* Send the command */
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->cmdarg, cmd->cmdarg);
|
2011-11-25 09:18:04 +09:00
|
|
|
#if defined(CONFIG_FSL_USDHC)
|
|
|
|
esdhc_write32(®s->mixctrl,
|
2015-01-21 00:16:44 +09:00
|
|
|
(esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
|
|
|
|
| (mmc->ddr_mode ? XFERTYP_DDREN : 0));
|
2011-11-25 09:18:04 +09:00
|
|
|
esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
|
|
|
|
#else
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->xfertyp, xfertyp);
|
2011-11-25 09:18:04 +09:00
|
|
|
#endif
|
2012-03-26 12:13:05 +09:00
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
/* Wait for the command to complete */
|
2012-03-26 12:13:05 +09:00
|
|
|
while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
|
2010-02-05 23:11:27 +09:00
|
|
|
;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
irqstat = esdhc_read32(®s->irqstat);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2014-03-24 16:41:06 +09:00
|
|
|
if (irqstat & CMD_ERR) {
|
2016-07-19 16:33:36 +09:00
|
|
|
err = -ECOMM;
|
2014-03-24 16:41:06 +09:00
|
|
|
goto out;
|
2012-03-26 12:13:05 +09:00
|
|
|
}
|
|
|
|
|
2014-03-24 16:41:06 +09:00
|
|
|
if (irqstat & IRQSTAT_CTOE) {
|
2016-07-19 16:33:36 +09:00
|
|
|
err = -ETIMEDOUT;
|
2014-03-24 16:41:06 +09:00
|
|
|
goto out;
|
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2015-02-17 21:42:43 +09:00
|
|
|
/* Switch voltage to 1.8V if CMD11 succeeded */
|
|
|
|
if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
|
|
|
|
esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
|
|
|
|
|
|
|
|
printf("Run CMD11 1.8V switch\n");
|
|
|
|
/* Sleep for 5 ms - max time for card to switch to 1.8V */
|
|
|
|
udelay(5000);
|
|
|
|
}
|
|
|
|
|
2012-03-26 12:13:05 +09:00
|
|
|
/* Workaround for ESDHC errata ENGcm03648 */
|
|
|
|
if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
|
2015-04-15 11:13:12 +09:00
|
|
|
int timeout = 6000;
|
2012-03-26 12:13:05 +09:00
|
|
|
|
2015-04-15 11:13:12 +09:00
|
|
|
/* Poll on DATA0 line for cmd with busy signal for 600 ms */
|
2012-03-26 12:13:05 +09:00
|
|
|
while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
|
|
|
|
PRSSTAT_DAT0)) {
|
|
|
|
udelay(100);
|
|
|
|
timeout--;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (timeout <= 0) {
|
|
|
|
printf("Timeout waiting for DAT0 to go high!\n");
|
2016-07-19 16:33:36 +09:00
|
|
|
err = -ETIMEDOUT;
|
2014-03-24 16:41:06 +09:00
|
|
|
goto out;
|
2012-03-26 12:13:05 +09:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
/* Copy the response to the response buffer */
|
|
|
|
if (cmd->resp_type & MMC_RSP_136) {
|
|
|
|
u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
|
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
cmdrsp3 = esdhc_read32(®s->cmdrsp3);
|
|
|
|
cmdrsp2 = esdhc_read32(®s->cmdrsp2);
|
|
|
|
cmdrsp1 = esdhc_read32(®s->cmdrsp1);
|
|
|
|
cmdrsp0 = esdhc_read32(®s->cmdrsp0);
|
2009-04-05 17:00:56 +09:00
|
|
|
cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
|
|
|
|
cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
|
|
|
|
cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
|
|
|
|
cmd->response[3] = (cmdrsp0 << 8);
|
2008-10-31 06:47:16 +09:00
|
|
|
} else
|
2010-02-05 23:11:27 +09:00
|
|
|
cmd->response[0] = esdhc_read32(®s->cmdrsp0);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Wait until all of the blocks are transferred */
|
|
|
|
if (data) {
|
2009-10-05 19:11:58 +09:00
|
|
|
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
|
2017-07-30 02:35:17 +09:00
|
|
|
esdhc_pio_read_write(priv, data);
|
2009-10-05 19:11:58 +09:00
|
|
|
#else
|
2008-10-31 06:47:16 +09:00
|
|
|
do {
|
2010-02-05 23:11:27 +09:00
|
|
|
irqstat = esdhc_read32(®s->irqstat);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2014-03-24 16:41:06 +09:00
|
|
|
if (irqstat & IRQSTAT_DTOE) {
|
2016-07-19 16:33:36 +09:00
|
|
|
err = -ETIMEDOUT;
|
2014-03-24 16:41:06 +09:00
|
|
|
goto out;
|
|
|
|
}
|
2010-07-31 13:45:18 +09:00
|
|
|
|
2014-03-24 16:41:06 +09:00
|
|
|
if (irqstat & DATA_ERR) {
|
2016-07-19 16:33:36 +09:00
|
|
|
err = -ECOMM;
|
2014-03-24 16:41:06 +09:00
|
|
|
goto out;
|
|
|
|
}
|
2013-04-08 08:06:08 +09:00
|
|
|
} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
|
2014-02-20 19:00:57 +09:00
|
|
|
|
2015-06-25 11:32:26 +09:00
|
|
|
/*
|
|
|
|
* Need invalidate the dcache here again to avoid any
|
|
|
|
* cache-fill during the DMA operations such as the
|
|
|
|
* speculative pre-fetching etc.
|
|
|
|
*/
|
2013-04-03 21:31:56 +09:00
|
|
|
if (data->flags & MMC_DATA_READ)
|
|
|
|
check_and_invalidate_dcache_range(cmd, data);
|
2014-02-20 19:00:57 +09:00
|
|
|
#endif
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
2014-03-24 16:41:06 +09:00
|
|
|
out:
|
|
|
|
/* Reset CMD and DATA portions on error */
|
|
|
|
if (err) {
|
|
|
|
esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
|
|
|
|
SYSCTL_RSTC);
|
|
|
|
while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
|
|
|
|
;
|
|
|
|
|
|
|
|
if (data) {
|
|
|
|
esdhc_write32(®s->sysctl,
|
|
|
|
esdhc_read32(®s->sysctl) |
|
|
|
|
SYSCTL_RSTD);
|
|
|
|
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
|
|
|
|
;
|
|
|
|
}
|
2015-02-17 21:42:43 +09:00
|
|
|
|
|
|
|
/* If this was CMD11, then notify that power cycle is needed */
|
|
|
|
if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
|
|
|
|
printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
|
2014-03-24 16:41:06 +09:00
|
|
|
}
|
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->irqstat, -1);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2014-03-24 16:41:06 +09:00
|
|
|
return err;
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:17 +09:00
|
|
|
static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
2017-05-03 18:59:03 +09:00
|
|
|
int div = 1;
|
|
|
|
#ifdef ARCH_MXC
|
|
|
|
int pre_div = 1;
|
|
|
|
#else
|
|
|
|
int pre_div = 2;
|
|
|
|
#endif
|
|
|
|
int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
|
int sdhc_clk = priv->sdhc_clk;
|
2008-10-31 06:47:16 +09:00
|
|
|
uint clk;
|
|
|
|
|
2014-03-12 02:34:20 +09:00
|
|
|
if (clock < mmc->cfg->f_min)
|
|
|
|
clock = mmc->cfg->f_min;
|
2010-02-05 23:11:27 +09:00
|
|
|
|
2017-05-03 18:59:03 +09:00
|
|
|
while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
|
|
|
|
pre_div *= 2;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2017-05-03 18:59:03 +09:00
|
|
|
while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
|
|
|
|
div++;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2017-05-03 18:59:03 +09:00
|
|
|
pre_div >>= 1;
|
2008-10-31 06:47:16 +09:00
|
|
|
div -= 1;
|
|
|
|
|
|
|
|
clk = (pre_div << 8) | (div << 4);
|
|
|
|
|
2015-12-05 04:32:48 +09:00
|
|
|
#ifdef CONFIG_FSL_USDHC
|
2016-06-15 11:53:01 +09:00
|
|
|
esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
|
2015-12-05 04:32:48 +09:00
|
|
|
#else
|
2010-03-19 05:51:05 +09:00
|
|
|
esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
|
2015-12-05 04:32:48 +09:00
|
|
|
#endif
|
2010-02-05 23:11:27 +09:00
|
|
|
|
|
|
|
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
udelay(10000);
|
|
|
|
|
2015-12-05 04:32:48 +09:00
|
|
|
#ifdef CONFIG_FSL_USDHC
|
2016-06-15 11:53:01 +09:00
|
|
|
esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
|
2015-12-05 04:32:48 +09:00
|
|
|
#else
|
|
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
|
|
|
|
#endif
|
2010-02-05 23:11:27 +09:00
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
2015-04-22 14:57:40 +09:00
|
|
|
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
2017-07-30 02:35:17 +09:00
|
|
|
static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
|
2015-04-22 14:57:40 +09:00
|
|
|
{
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2015-04-22 14:57:40 +09:00
|
|
|
u32 value;
|
|
|
|
u32 time_out;
|
|
|
|
|
|
|
|
value = esdhc_read32(®s->sysctl);
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
value |= SYSCTL_CKEN;
|
|
|
|
else
|
|
|
|
value &= ~SYSCTL_CKEN;
|
|
|
|
|
|
|
|
esdhc_write32(®s->sysctl, value);
|
|
|
|
|
|
|
|
time_out = 20;
|
|
|
|
value = PRSSTAT_SDSTB;
|
|
|
|
while (!(esdhc_read32(®s->prsstat) & value)) {
|
|
|
|
if (time_out == 0) {
|
|
|
|
printf("fsl_esdhc: Internal clock never stabilised.\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
time_out--;
|
|
|
|
mdelay(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-07-30 02:35:18 +09:00
|
|
|
static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2015-04-22 14:57:40 +09:00
|
|
|
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
|
|
|
/* Select to use peripheral clock */
|
2017-07-30 02:35:17 +09:00
|
|
|
esdhc_clock_control(priv, false);
|
2015-04-22 14:57:40 +09:00
|
|
|
esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
|
2017-07-30 02:35:17 +09:00
|
|
|
esdhc_clock_control(priv, true);
|
2015-04-22 14:57:40 +09:00
|
|
|
#endif
|
2008-10-31 06:47:16 +09:00
|
|
|
/* Set the clock speed */
|
2017-07-30 02:35:17 +09:00
|
|
|
set_sysctl(priv, mmc, mmc->clock);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Set the bus width */
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
if (mmc->bus_width == 4)
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
|
2008-10-31 06:47:16 +09:00
|
|
|
else if (mmc->bus_width == 8)
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
|
|
|
|
|
2016-12-30 15:30:16 +09:00
|
|
|
return 0;
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:18 +09:00
|
|
|
static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2017-07-30 02:35:20 +09:00
|
|
|
ulong start;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
/* Reset the entire host controller */
|
2013-07-15 22:44:29 +09:00
|
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
|
2010-02-05 23:11:27 +09:00
|
|
|
|
|
|
|
/* Wait until the controller is available */
|
2017-07-30 02:35:20 +09:00
|
|
|
start = get_timer(0);
|
|
|
|
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
|
|
|
|
if (get_timer(start) > 1000)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2016-06-15 11:53:00 +09:00
|
|
|
#if defined(CONFIG_FSL_USDHC)
|
|
|
|
/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
|
|
|
|
esdhc_write32(®s->mmcboot, 0x0);
|
|
|
|
/* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
|
|
|
|
esdhc_write32(®s->mixctrl, 0x0);
|
|
|
|
esdhc_write32(®s->clktunectrlstatus, 0x0);
|
|
|
|
|
|
|
|
/* Put VEND_SPEC to default value */
|
|
|
|
esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
|
|
|
|
|
|
|
|
/* Disable DLL_CTRL delay line */
|
|
|
|
esdhc_write32(®s->dllctrl, 0x0);
|
|
|
|
#endif
|
|
|
|
|
2012-08-13 16:28:16 +09:00
|
|
|
#ifndef ARCH_MXC
|
2010-12-04 14:07:23 +09:00
|
|
|
/* Enable cache snooping */
|
2012-08-13 16:28:16 +09:00
|
|
|
esdhc_write32(®s->scr, 0x00000040);
|
|
|
|
#endif
|
2010-12-04 14:07:23 +09:00
|
|
|
|
2015-12-05 04:32:48 +09:00
|
|
|
#ifndef CONFIG_FSL_USDHC
|
2013-07-15 22:44:29 +09:00
|
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
|
2016-06-15 11:53:01 +09:00
|
|
|
#else
|
|
|
|
esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
|
2015-12-05 04:32:48 +09:00
|
|
|
#endif
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Set the initial clock speed */
|
2017-09-21 23:30:03 +09:00
|
|
|
mmc_set_clock(mmc, 400000, false);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Disable the BRR and BWR bits in IRQSTAT */
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Put the PROCTL reg back to the default */
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->proctl, PROCTL_INIT);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
/* Set timout to the maximum value */
|
|
|
|
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2017-06-12 18:50:53 +09:00
|
|
|
if (priv->vs18_enable)
|
|
|
|
esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
|
|
|
|
|
2012-01-02 10:15:38 +09:00
|
|
|
return 0;
|
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2017-07-30 02:35:18 +09:00
|
|
|
static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
|
2012-01-02 10:15:38 +09:00
|
|
|
{
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2012-01-02 10:15:38 +09:00
|
|
|
int timeout = 1000;
|
|
|
|
|
2014-01-10 14:52:17 +09:00
|
|
|
#ifdef CONFIG_ESDHC_DETECT_QUIRK
|
|
|
|
if (CONFIG_ESDHC_DETECT_QUIRK)
|
|
|
|
return 1;
|
|
|
|
#endif
|
2016-03-25 15:16:56 +09:00
|
|
|
|
2017-07-30 02:35:24 +09:00
|
|
|
#if CONFIG_IS_ENABLED(DM_MMC)
|
2016-03-25 15:16:56 +09:00
|
|
|
if (priv->non_removable)
|
|
|
|
return 1;
|
2016-12-07 12:54:30 +09:00
|
|
|
#ifdef CONFIG_DM_GPIO
|
2016-03-25 15:16:56 +09:00
|
|
|
if (dm_gpio_is_valid(&priv->cd_gpio))
|
|
|
|
return dm_gpio_get_value(&priv->cd_gpio);
|
2016-12-07 12:54:30 +09:00
|
|
|
#endif
|
2016-03-25 15:16:56 +09:00
|
|
|
#endif
|
|
|
|
|
2012-01-02 10:15:38 +09:00
|
|
|
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
|
|
|
|
udelay(1000);
|
2010-02-05 23:11:27 +09:00
|
|
|
|
2012-01-02 10:15:38 +09:00
|
|
|
return timeout > 0;
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:19 +09:00
|
|
|
static int esdhc_reset(struct fsl_esdhc *regs)
|
2010-03-19 05:57:06 +09:00
|
|
|
{
|
2017-07-30 02:35:19 +09:00
|
|
|
ulong start;
|
2010-03-19 05:57:06 +09:00
|
|
|
|
|
|
|
/* reset the controller */
|
2013-07-15 22:44:29 +09:00
|
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
|
2010-03-19 05:57:06 +09:00
|
|
|
|
|
|
|
/* hardware clears the bit when it is done */
|
2017-07-30 02:35:19 +09:00
|
|
|
start = get_timer(0);
|
|
|
|
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
|
|
|
|
if (get_timer(start) > 100) {
|
|
|
|
printf("MMC/SD: Reset never completed.\n");
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2010-03-19 05:57:06 +09:00
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:31 +09:00
|
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
2017-07-30 02:35:18 +09:00
|
|
|
static int esdhc_getcd(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
|
|
|
|
|
return esdhc_getcd_common(priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int esdhc_init(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
|
|
|
|
|
return esdhc_init_common(priv, mmc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
|
|
|
|
struct mmc_data *data)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
|
|
|
|
|
return esdhc_send_cmd_common(priv, mmc, cmd, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int esdhc_set_ios(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
|
|
|
|
|
return esdhc_set_ios_common(priv, mmc);
|
|
|
|
}
|
|
|
|
|
2014-02-27 02:28:45 +09:00
|
|
|
static const struct mmc_ops esdhc_ops = {
|
2017-07-30 02:35:18 +09:00
|
|
|
.getcd = esdhc_getcd,
|
|
|
|
.init = esdhc_init,
|
2014-02-27 02:28:45 +09:00
|
|
|
.send_cmd = esdhc_send_cmd,
|
|
|
|
.set_ios = esdhc_set_ios,
|
|
|
|
};
|
2017-07-30 02:35:24 +09:00
|
|
|
#endif
|
2014-02-27 02:28:45 +09:00
|
|
|
|
2017-07-30 02:35:21 +09:00
|
|
|
static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
|
|
|
|
struct fsl_esdhc_plat *plat)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
2017-07-30 02:35:21 +09:00
|
|
|
struct mmc_config *cfg;
|
2010-02-05 23:11:27 +09:00
|
|
|
struct fsl_esdhc *regs;
|
2010-11-26 02:06:09 +09:00
|
|
|
u32 caps, voltage_caps;
|
2017-07-30 02:35:19 +09:00
|
|
|
int ret;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
if (!priv)
|
|
|
|
return -EINVAL;
|
2010-02-05 23:11:27 +09:00
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
regs = priv->esdhc_regs;
|
2010-02-05 23:11:27 +09:00
|
|
|
|
2010-03-19 05:57:06 +09:00
|
|
|
/* First reset the eSDHC controller */
|
2017-07-30 02:35:19 +09:00
|
|
|
ret = esdhc_reset(regs);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-03-19 05:57:06 +09:00
|
|
|
|
2015-12-05 04:32:48 +09:00
|
|
|
#ifndef CONFIG_FSL_USDHC
|
2012-05-18 08:57:02 +09:00
|
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
|
|
|
|
| SYSCTL_IPGEN | SYSCTL_CKEN);
|
2016-06-15 11:53:01 +09:00
|
|
|
#else
|
|
|
|
esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
|
|
|
|
VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
|
2015-12-05 04:32:48 +09:00
|
|
|
#endif
|
2012-05-18 08:57:02 +09:00
|
|
|
|
2017-06-12 18:50:53 +09:00
|
|
|
if (priv->vs18_enable)
|
|
|
|
esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
|
|
|
|
|
2014-11-04 16:35:49 +09:00
|
|
|
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg = &plat->cfg;
|
2017-07-30 02:35:24 +09:00
|
|
|
#ifndef CONFIG_DM_MMC
|
2017-07-30 02:35:21 +09:00
|
|
|
memset(cfg, '\0', sizeof(*cfg));
|
2017-07-30 02:35:24 +09:00
|
|
|
#endif
|
2014-03-12 02:34:20 +09:00
|
|
|
|
2010-11-26 02:06:09 +09:00
|
|
|
voltage_caps = 0;
|
2014-09-05 14:52:40 +09:00
|
|
|
caps = esdhc_read32(®s->hostcapblt);
|
2011-01-07 15:06:47 +09:00
|
|
|
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
|
|
|
|
caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
|
|
|
|
ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
|
|
|
|
#endif
|
2013-10-31 10:38:19 +09:00
|
|
|
|
|
|
|
/* T4240 host controller capabilities register should have VS33 bit */
|
|
|
|
#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
|
|
|
caps = caps | ESDHC_HOSTCAPBLT_VS33;
|
|
|
|
#endif
|
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
if (caps & ESDHC_HOSTCAPBLT_VS18)
|
2010-11-26 02:06:09 +09:00
|
|
|
voltage_caps |= MMC_VDD_165_195;
|
2008-10-31 06:47:16 +09:00
|
|
|
if (caps & ESDHC_HOSTCAPBLT_VS30)
|
2010-11-26 02:06:09 +09:00
|
|
|
voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
|
2008-10-31 06:47:16 +09:00
|
|
|
if (caps & ESDHC_HOSTCAPBLT_VS33)
|
2010-11-26 02:06:09 +09:00
|
|
|
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
|
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->name = "FSL_SDHC";
|
2017-07-30 02:35:31 +09:00
|
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->ops = &esdhc_ops;
|
2017-07-30 02:35:24 +09:00
|
|
|
#endif
|
2010-11-26 02:06:09 +09:00
|
|
|
#ifdef CONFIG_SYS_SD_VOLTAGE
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
|
2010-11-26 02:06:09 +09:00
|
|
|
#else
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
2010-11-26 02:06:09 +09:00
|
|
|
#endif
|
2017-07-30 02:35:21 +09:00
|
|
|
if ((cfg->voltages & voltage_caps) == 0) {
|
2010-11-26 02:06:09 +09:00
|
|
|
printf("voltage not supported by controller\n");
|
|
|
|
return -1;
|
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
if (priv->bus_width == 8)
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
|
2016-03-25 15:16:56 +09:00
|
|
|
else if (priv->bus_width == 4)
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->host_caps = MMC_MODE_4BIT;
|
2016-03-25 15:16:56 +09:00
|
|
|
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
|
2015-01-21 00:16:44 +09:00
|
|
|
#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->host_caps |= MMC_MODE_DDR_52MHz;
|
2015-01-21 00:16:44 +09:00
|
|
|
#endif
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
if (priv->bus_width > 0) {
|
|
|
|
if (priv->bus_width < 8)
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->host_caps &= ~MMC_MODE_8BIT;
|
2016-03-25 15:16:56 +09:00
|
|
|
if (priv->bus_width < 4)
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->host_caps &= ~MMC_MODE_4BIT;
|
2013-03-25 18:13:34 +09:00
|
|
|
}
|
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
if (caps & ESDHC_HOSTCAPBLT_HSS)
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2014-01-10 14:52:18 +09:00
|
|
|
#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
|
|
|
|
if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->host_caps &= ~MMC_MODE_8BIT;
|
2014-01-10 14:52:18 +09:00
|
|
|
#endif
|
|
|
|
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->f_min = 400000;
|
|
|
|
cfg->f_max = min(priv->sdhc_clk, (u32)52000000);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
2014-03-12 02:34:20 +09:00
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:28 +09:00
|
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
2017-05-12 20:48:20 +09:00
|
|
|
static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
|
|
|
|
struct fsl_esdhc_priv *priv)
|
|
|
|
{
|
|
|
|
if (!cfg || !priv)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
|
|
|
|
priv->bus_width = cfg->max_bus_width;
|
|
|
|
priv->sdhc_clk = cfg->sdhc_clk;
|
|
|
|
priv->wp_enable = cfg->wp_enable;
|
2017-06-12 18:50:53 +09:00
|
|
|
priv->vs18_enable = cfg->vs18_enable;
|
2017-05-12 20:48:20 +09:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
};
|
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
|
|
|
|
{
|
2017-07-30 02:35:21 +09:00
|
|
|
struct fsl_esdhc_plat *plat;
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc_priv *priv;
|
2017-07-30 02:35:22 +09:00
|
|
|
struct mmc *mmc;
|
2016-03-25 15:16:56 +09:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!cfg)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
|
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
2017-07-30 02:35:21 +09:00
|
|
|
plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
|
|
|
|
if (!plat) {
|
|
|
|
free(priv);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2016-03-25 15:16:56 +09:00
|
|
|
|
|
|
|
ret = fsl_esdhc_cfg_to_priv(cfg, priv);
|
|
|
|
if (ret) {
|
|
|
|
debug("%s xlate failure\n", __func__);
|
2017-07-30 02:35:21 +09:00
|
|
|
free(plat);
|
2016-03-25 15:16:56 +09:00
|
|
|
free(priv);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:21 +09:00
|
|
|
ret = fsl_esdhc_init(priv, plat);
|
2016-03-25 15:16:56 +09:00
|
|
|
if (ret) {
|
|
|
|
debug("%s init failure\n", __func__);
|
2017-07-30 02:35:21 +09:00
|
|
|
free(plat);
|
2016-03-25 15:16:56 +09:00
|
|
|
free(priv);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:22 +09:00
|
|
|
mmc = mmc_create(&plat->cfg, priv);
|
|
|
|
if (!mmc)
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
priv->mmc = mmc;
|
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int fsl_esdhc_mmc_init(bd_t *bis)
|
|
|
|
{
|
2010-02-05 23:11:27 +09:00
|
|
|
struct fsl_esdhc_cfg *cfg;
|
|
|
|
|
2012-12-27 17:51:08 +09:00
|
|
|
cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
|
2010-02-05 23:11:27 +09:00
|
|
|
cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
|
2012-12-14 05:49:05 +09:00
|
|
|
cfg->sdhc_clk = gd->arch.sdhc_clk;
|
2010-02-05 23:11:27 +09:00
|
|
|
return fsl_esdhc_initialize(bis, cfg);
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
2017-05-12 20:48:20 +09:00
|
|
|
#endif
|
2009-06-10 05:25:29 +09:00
|
|
|
|
2015-04-22 14:57:00 +09:00
|
|
|
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
|
|
|
|
void mmc_adapter_card_type_ident(void)
|
|
|
|
{
|
|
|
|
u8 card_id;
|
|
|
|
u8 value;
|
|
|
|
|
|
|
|
card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
|
|
|
|
gd->arch.sdhc_adapter = card_id;
|
|
|
|
|
|
|
|
switch (card_id) {
|
|
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
|
2015-09-17 11:27:12 +09:00
|
|
|
value = QIXIS_READ(brdcfg[5]);
|
|
|
|
value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
|
|
|
|
QIXIS_WRITE(brdcfg[5], value);
|
2015-04-22 14:57:00 +09:00
|
|
|
break;
|
|
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
|
2015-09-17 11:27:48 +09:00
|
|
|
value = QIXIS_READ(pwr_ctl[1]);
|
|
|
|
value |= QIXIS_EVDD_BY_SDHC_VS;
|
|
|
|
QIXIS_WRITE(pwr_ctl[1], value);
|
2015-04-22 14:57:00 +09:00
|
|
|
break;
|
|
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
|
|
|
|
value = QIXIS_READ(brdcfg[5]);
|
|
|
|
value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
|
|
|
|
QIXIS_WRITE(brdcfg[5], value);
|
|
|
|
break;
|
|
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
|
|
|
|
break;
|
|
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
|
|
|
|
break;
|
|
|
|
case QIXIS_ESDHC_ADAPTER_TYPE_SD:
|
|
|
|
break;
|
|
|
|
case QIXIS_ESDHC_NO_ADAPTER:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
#ifdef CONFIG_OF_LIBFDT
|
2017-01-17 11:43:54 +09:00
|
|
|
__weak int esdhc_status_fixup(void *blob, const char *compat)
|
2009-06-10 05:25:29 +09:00
|
|
|
{
|
2011-01-04 18:23:05 +09:00
|
|
|
#ifdef CONFIG_FSL_ESDHC_PIN_MUX
|
2009-06-10 05:25:29 +09:00
|
|
|
if (!hwconfig("esdhc")) {
|
2011-01-04 18:23:05 +09:00
|
|
|
do_fixup_by_compat(blob, compat, "status", "disabled",
|
2017-01-17 11:43:54 +09:00
|
|
|
sizeof("disabled"), 1);
|
|
|
|
return 1;
|
2009-06-10 05:25:29 +09:00
|
|
|
}
|
2011-01-04 18:23:05 +09:00
|
|
|
#endif
|
2017-01-17 11:43:54 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void fdt_fixup_esdhc(void *blob, bd_t *bd)
|
|
|
|
{
|
|
|
|
const char *compat = "fsl,esdhc";
|
|
|
|
|
|
|
|
if (esdhc_status_fixup(blob, compat))
|
|
|
|
return;
|
2009-06-10 05:25:29 +09:00
|
|
|
|
2015-04-22 14:57:40 +09:00
|
|
|
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
|
|
|
do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
|
|
|
|
gd->arch.sdhc_clk, 1);
|
|
|
|
#else
|
2009-06-10 05:25:29 +09:00
|
|
|
do_fixup_by_compat_u32(blob, compat, "clock-frequency",
|
2012-12-14 05:49:05 +09:00
|
|
|
gd->arch.sdhc_clk, 1);
|
2015-04-22 14:57:40 +09:00
|
|
|
#endif
|
2015-04-22 14:57:00 +09:00
|
|
|
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
|
|
|
|
do_fixup_by_compat_u32(blob, compat, "adapter-type",
|
|
|
|
(u32)(gd->arch.sdhc_adapter), 1);
|
|
|
|
#endif
|
2009-06-10 05:25:29 +09:00
|
|
|
}
|
2010-02-05 23:11:27 +09:00
|
|
|
#endif
|
2016-03-25 15:16:56 +09:00
|
|
|
|
2017-07-30 02:35:24 +09:00
|
|
|
#if CONFIG_IS_ENABLED(DM_MMC)
|
2016-03-25 15:16:56 +09:00
|
|
|
#include <asm/arch/clock.h>
|
2017-02-22 17:21:55 +09:00
|
|
|
__weak void init_clk_usdhc(u32 index)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
static int fsl_esdhc_probe(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
2017-07-30 02:35:21 +09:00
|
|
|
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
2017-08-09 07:45:13 +09:00
|
|
|
#ifdef CONFIG_DM_REGULATOR
|
2017-06-12 18:50:54 +09:00
|
|
|
struct udevice *vqmmc_dev;
|
2017-08-09 07:45:13 +09:00
|
|
|
#endif
|
2016-03-25 15:16:56 +09:00
|
|
|
fdt_addr_t addr;
|
|
|
|
unsigned int val;
|
2017-07-30 02:35:24 +09:00
|
|
|
struct mmc *mmc;
|
2016-03-25 15:16:56 +09:00
|
|
|
int ret;
|
|
|
|
|
2017-07-30 02:35:23 +09:00
|
|
|
addr = dev_read_addr(dev);
|
2016-03-25 15:16:56 +09:00
|
|
|
if (addr == FDT_ADDR_T_NONE)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
priv->esdhc_regs = (struct fsl_esdhc *)addr;
|
|
|
|
priv->dev = dev;
|
|
|
|
|
2017-07-30 02:35:23 +09:00
|
|
|
val = dev_read_u32_default(dev, "bus-width", -1);
|
2016-03-25 15:16:56 +09:00
|
|
|
if (val == 8)
|
|
|
|
priv->bus_width = 8;
|
|
|
|
else if (val == 4)
|
|
|
|
priv->bus_width = 4;
|
|
|
|
else
|
|
|
|
priv->bus_width = 1;
|
|
|
|
|
2017-07-30 02:35:23 +09:00
|
|
|
if (dev_read_bool(dev, "non-removable")) {
|
2016-03-25 15:16:56 +09:00
|
|
|
priv->non_removable = 1;
|
|
|
|
} else {
|
|
|
|
priv->non_removable = 0;
|
2016-12-07 12:54:30 +09:00
|
|
|
#ifdef CONFIG_DM_GPIO
|
2017-07-30 02:35:23 +09:00
|
|
|
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
|
|
|
|
GPIOD_IS_IN);
|
2016-12-07 12:54:30 +09:00
|
|
|
#endif
|
2016-03-25 15:16:56 +09:00
|
|
|
}
|
|
|
|
|
mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-15 11:53:02 +09:00
|
|
|
priv->wp_enable = 1;
|
|
|
|
|
2016-12-07 12:54:30 +09:00
|
|
|
#ifdef CONFIG_DM_GPIO
|
2017-07-30 02:35:23 +09:00
|
|
|
ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
|
|
|
|
GPIOD_IS_IN);
|
mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-15 11:53:02 +09:00
|
|
|
if (ret)
|
|
|
|
priv->wp_enable = 0;
|
2016-12-07 12:54:30 +09:00
|
|
|
#endif
|
2017-06-12 18:50:54 +09:00
|
|
|
|
|
|
|
priv->vs18_enable = 0;
|
|
|
|
|
|
|
|
#ifdef CONFIG_DM_REGULATOR
|
|
|
|
/*
|
|
|
|
* If emmc I/O has a fixed voltage at 1.8V, this must be provided,
|
|
|
|
* otherwise, emmc will work abnormally.
|
|
|
|
*/
|
|
|
|
ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_dbg(dev, "no vqmmc-supply\n");
|
|
|
|
} else {
|
|
|
|
ret = regulator_set_enable(vqmmc_dev, true);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "fail to enable vqmmc-supply\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (regulator_get_value(vqmmc_dev) == 1800000)
|
|
|
|
priv->vs18_enable = 1;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
/*
|
|
|
|
* TODO:
|
|
|
|
* Because lack of clk driver, if SDHC clk is not enabled,
|
|
|
|
* need to enable it first before this driver is invoked.
|
|
|
|
*
|
|
|
|
* we use MXC_ESDHC_CLK to get clk freq.
|
|
|
|
* If one would like to make this function work,
|
|
|
|
* the aliases should be provided in dts as this:
|
|
|
|
*
|
|
|
|
* aliases {
|
|
|
|
* mmc0 = &usdhc1;
|
|
|
|
* mmc1 = &usdhc2;
|
|
|
|
* mmc2 = &usdhc3;
|
|
|
|
* mmc3 = &usdhc4;
|
|
|
|
* };
|
|
|
|
* Then if your board only supports mmc2 and mmc3, but we can
|
|
|
|
* correctly get the seq as 2 and 3, then let mxc_get_clock
|
|
|
|
* work as expected.
|
|
|
|
*/
|
2017-02-22 17:21:55 +09:00
|
|
|
|
|
|
|
init_clk_usdhc(dev->seq);
|
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
|
|
|
|
if (priv->sdhc_clk <= 0) {
|
|
|
|
dev_err(dev, "Unable to get clk for %s\n", dev->name);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:21 +09:00
|
|
|
ret = fsl_esdhc_init(priv, plat);
|
2016-03-25 15:16:56 +09:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "fsl_esdhc_init failure\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:24 +09:00
|
|
|
mmc = &plat->mmc;
|
|
|
|
mmc->cfg = &plat->cfg;
|
|
|
|
mmc->dev = dev;
|
|
|
|
upriv->mmc = mmc;
|
2016-03-25 15:16:56 +09:00
|
|
|
|
2017-07-30 02:35:24 +09:00
|
|
|
return esdhc_init_common(priv, mmc);
|
2016-03-25 15:16:56 +09:00
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:31 +09:00
|
|
|
#if CONFIG_IS_ENABLED(DM_MMC)
|
2017-07-30 02:35:24 +09:00
|
|
|
static int fsl_esdhc_get_cd(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
return esdhc_getcd_common(priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
|
|
|
|
struct mmc_data *data)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
|
|
|
|
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_esdhc_set_ios(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
|
|
|
|
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
return esdhc_set_ios_common(priv, &plat->mmc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dm_mmc_ops fsl_esdhc_ops = {
|
|
|
|
.get_cd = fsl_esdhc_get_cd,
|
|
|
|
.send_cmd = fsl_esdhc_send_cmd,
|
|
|
|
.set_ios = fsl_esdhc_set_ios,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
static const struct udevice_id fsl_esdhc_ids[] = {
|
|
|
|
{ .compatible = "fsl,imx6ul-usdhc", },
|
|
|
|
{ .compatible = "fsl,imx6sx-usdhc", },
|
|
|
|
{ .compatible = "fsl,imx6sl-usdhc", },
|
|
|
|
{ .compatible = "fsl,imx6q-usdhc", },
|
|
|
|
{ .compatible = "fsl,imx7d-usdhc", },
|
2017-02-22 17:21:55 +09:00
|
|
|
{ .compatible = "fsl,imx7ulp-usdhc", },
|
2016-12-07 12:54:31 +09:00
|
|
|
{ .compatible = "fsl,esdhc", },
|
2016-03-25 15:16:56 +09:00
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
|
2017-07-30 02:35:24 +09:00
|
|
|
#if CONFIG_IS_ENABLED(BLK)
|
|
|
|
static int fsl_esdhc_bind(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
|
|
|
|
|
|
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
U_BOOT_DRIVER(fsl_esdhc) = {
|
|
|
|
.name = "fsl-esdhc-mmc",
|
|
|
|
.id = UCLASS_MMC,
|
|
|
|
.of_match = fsl_esdhc_ids,
|
2017-07-30 02:35:24 +09:00
|
|
|
.ops = &fsl_esdhc_ops,
|
|
|
|
#if CONFIG_IS_ENABLED(BLK)
|
|
|
|
.bind = fsl_esdhc_bind,
|
|
|
|
#endif
|
2016-03-25 15:16:56 +09:00
|
|
|
.probe = fsl_esdhc_probe,
|
2017-07-30 02:35:21 +09:00
|
|
|
.platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
|
2016-03-25 15:16:56 +09:00
|
|
|
.priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
|
|
|
|
};
|
|
|
|
#endif
|