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0ca4c0b672
[ Upstream commit9846a4524a] Recent changes to the atheros at803x driver caused ethernet to stop working on this board. In particular commit6d4cd041f0("net: phy: at803x: disable delay only for RGMII mode") and commitcd28d1d6e5("net: phy: at803x: Disable phy delay for RGMII mode") fix the AR8031 driver to configure the phy's (RX/TX) delays as per the 'phy-mode' in the device tree. This now prevents ethernet from working on this board. It used to work before those commits, because the AR8031 comes out of reset with RX delay enabled, and the at803x driver didn't touch the delay configuration at all when "rgmii" mode was selected, and because arch/arm/mach-imx/mach-imx7d.c:ar8031_phy_fixup() unconditionally enables TX delay. Since above commits ar8031_phy_fixup() also has no effect anymore, and the end-result is that all delays are disabled in the phy, no ethernet. Update the device tree to restore functionality. Signed-off-by: André Draszik <git@andred.net> CC: Ilya Ledvich <ilya@compulab.co.il> CC: Igor Grinberg <grinberg@compulab.co.il> CC: Rob Herring <robh+dt@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> CC: Shawn Guo <shawnguo@kernel.org> CC: Sascha Hauer <s.hauer@pengutronix.de> CC: Pengutronix Kernel Team <kernel@pengutronix.de> CC: Fabio Estevam <festevam@gmail.com> CC: NXP Linux Team <linux-imx@nxp.com> CC: devicetree@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
287 lines
6.7 KiB
Plaintext
287 lines
6.7 KiB
Plaintext
/*
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* Support for CompuLab CL-SOM-iMX7 System-on-Module
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*
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* Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
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* Author: Ilya Ledvich <ilya@compulab.co.il>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*/
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/dts-v1/;
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#include "imx7d.dtsi"
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/ {
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model = "CompuLab CL-SOM-iMX7";
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compatible = "compulab,cl-som-imx7", "fsl,imx7d";
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memory {
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reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */
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};
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reg_usb_otg1_vbus: regulator-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&cpu0 {
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arm-supply = <&sw1a_reg>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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pmic: pmic@8 {
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compatible = "fsl,pfuze3000";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1a {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* use sw1c_reg to align with pfuze100/pfuze200 */
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sw1c_reg: sw1b {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a_reg: sw3 {
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1650000>;
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regulator-boot-on;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1_reg: vldo1 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen2_reg: vldo2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen3_reg: vccsd {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: v33 {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vldo3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vldo4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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pca9555: pca9555@20 {
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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};
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eeprom@50 {
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compatible = "atmel,24c08";
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reg = <0x50>;
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pagesize = <16>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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status = "okay";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1>;
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vbus-supply = <®_usb_otg1_vbus>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3>;
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assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
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assigned-clock-rates = <400000000>;
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bus-width = <8>;
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fsl,tuning-step = <2>;
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non-removable;
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status = "okay";
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};
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&iomuxc {
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x30
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MX7D_PAD_SD2_WP__ENET1_MDC 0x30
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x11
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x11
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x11
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x11
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x11
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x11
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x11
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x11
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MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x11
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MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x11
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MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x11
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MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x11
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MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x11
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MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x11
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MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x11
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MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x11
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MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x11
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MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x11
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MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x11
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
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MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
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MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX7D_PAD_SD3_CMD__SD3_CMD 0x59
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MX7D_PAD_SD3_CLK__SD3_CLK 0x19
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MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
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MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
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MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
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MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
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MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
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MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
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MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
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MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
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MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
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>;
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};
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};
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&iomuxc_lpsr {
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pinctrl_usbotg1: usbotg1grp {
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fsl,pins = <
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MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */
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>;
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};
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}; |